Release 9.1i - netgen J.30Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.Command Line: netgen -intstyle ise -s 7 -pcf sjall.pcf -rpw 100 -tpw 0 -ar
Structure -tm sjall -w -dir netgen/map -ofmt vhdl -sim sjall_map.ncd
sjall_map.vhd  Read and Annotate design 'sjall_map.ncd' ...Loading device for application Rf_Device from file '2s50e.nph' in environment
C:\Xilinx91i.   "sjall" is an NCD, version 3.1, device xc2s50e, package tq144, speed -7Loading constraints from 'sjall.pcf'...The speed grade (-7) differs from the speed grade specified in the .ncd file
(-7).The number of routable networks is 310Flattening design ...Processing design ...   Preping design's networks ...  Preping design's macros ...Writing VHDL netlist 'E:\Application\SJ\FPGA\netgen\map\sjall_map.vhd' ...Writing VHDL SDF file 'E:\Application\SJ\FPGA\netgen\map\sjall_map.sdf' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM library for correct
   compilation and simulation. Number of warnings: 0Number of info messages: 1Total memory usage is 102172 kilobytes