Release 9.1i - netgen J.30Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.Command Line: netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm sjall -w
-dir netgen/translate -ofmt vhdl -sim sjall.ngd sjall_translate.vhd  Reading design 'sjall.ngd' ...Flattening design ...Processing design ...   Preping design's networks ...  Preping design's macros ...Writing VHDL netlist
'E:\Application\SJ\FPGA\netgen\translate\sjall_translate.vhd' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM library for correct
   compilation and simulation. Number of warnings: 0Number of info messages: 1Total memory usage is 67392 kilobytes