?? sjall_translate.vhd
字號(hào):
port map ( I0 => XLXI_3_XLXN_142, I1 => XLXI_3_XLXN_141, O => XLXI_3_XLXN_251 ); XLXI_3_XLXI_233 : X_AND2 port map ( I0 => XLXI_3_XLXN_228, I1 => XLXI_3_XLXN_227, O => XLXI_3_XLXN_252 ); XLXI_3_XLXI_232 : X_OR2 port map ( I0 => XLXI_3_XLXN_252, I1 => clk_40_BUFGP, O => XLXI_3_XLXN_265 ); XLXI_3_XLXI_231 : X_OR2 port map ( I0 => XLXI_3_XLXN_251, I1 => clk_40_BUFGP, O => XLXI_3_XLXN_260 ); XLXI_3_XLXI_230 : X_OR2 port map ( I0 => XLXI_3_XLXN_242, I1 => XLXI_3_XLXN_241, O => NlwInverterSignal_XLXI_3_XLXI_230_O ); XLXI_3_XLXI_229 : X_INV port map ( I => XLXI_3_XLXN_241, O => XLXN_29 ); XLXI_3_XLXI_223 : X_AND2 port map ( I0 => XLXI_3_XLXN_137, I1 => XLXI_3_XLXN_38, O => XLXI_3_XLXN_469 ); XLXI_3_XLXI_222 : X_AND2 port map ( I0 => XLXI_3_XLXN_39, I1 => XLXI_3_XLXN_48, O => XLXI_3_XLXN_465 ); XLXI_3_XLXI_111 : X_OR2 port map ( I0 => XLXI_3_XLXN_221, I1 => vref_OBUF_14, O => XLXI_3_XLXN_580 ); XLXI_3_XLXI_107 : X_AND2 port map ( I0 => XLXI_3_XLXN_224, I1 => XLXI_3_XLXN_223, O => XLXI_3_XLXN_581 ); XLXI_3_XLXI_106 : X_AND2 port map ( I0 => XLXI_3_XLXN_220, I1 => XLXI_3_XLXN_219, O => XLXI_3_XLXN_221 ); XLXI_3_XLXI_105 : X_AND2 port map ( I0 => XLXI_3_XLXN_602, I1 => XLXI_3_XLXN_601, O => vref_OBUF_14 ); XLXI_3_XLXI_104 : X_AND5 port map ( I0 => XLXI_3_XLXN_154, I1 => XLXI_3_XLXN_150, I2 => XLXI_3_XLXN_148, I3 => XLXI_3_XLXN_24, I4 => XLXI_3_XLXN_23, O => XLXI_3_XLXN_219 ); XLXI_3_XLXI_103 : X_OR5 port map ( I0 => XLXI_3_XLXN_152, I1 => XLXI_3_XLXN_151, I2 => XLXI_3_XLXN_147, I3 => XLXI_3_XLXN_22, I4 => XLXI_3_XLXN_21, O => NlwInverterSignal_XLXI_3_XLXI_103_O ); XLXI_3_XLXI_96 : X_OR5 port map ( I0 => XLXI_3_XLXN_22, I1 => XLXI_3_XLXN_23, I2 => XLXI_3_XLXN_24, I3 => XLXI_3_XLXN_151, I4 => XLXI_3_XLXN_152, O => NlwInverterSignal_XLXI_3_XLXI_96_O ); XLXI_3_XLXI_92 : X_AND5 port map ( I0 => XLXI_3_XLXN_21, I1 => XLXI_3_XLXN_147, I2 => XLXI_3_XLXN_148, I3 => XLXI_3_XLXN_150, I4 => XLXI_3_XLXN_154, O => XLXI_3_XLXN_227 ); XLXI_3_XLXI_90 : X_AND4 port map ( I0 => XLXI_3_XLXN_148, I1 => XLXI_3_XLXN_24, I2 => XLXI_3_XLXN_23, I3 => XLXI_3_XLXN_21, O => XLXI_3_XLXN_223 XLXI_3_XLXI_63 : X_OR5 port map ( I0 => XLXI_3_XLXN_154, I1 => XLXI_3_XLXN_152, I2 => XLXI_3_XLXN_151, I3 => XLXI_3_XLXN_150, I4 => XLXI_3_XLXN_148, O => NlwInverterSignal_XLXI_3_XLXI_63_O ); XLXI_3_XLXI_62 : X_OR5 port map ( I0 => XLXI_3_XLXN_147, I1 => XLXI_3_XLXN_24, I2 => XLXI_3_XLXN_23, I3 => XLXI_3_XLXN_22, I4 => XLXI_3_XLXN_21, O => NlwInverterSignal_XLXI_3_XLXI_62_O ); XLXI_3_XLXI_58 : X_AND4 port map ( I0 => XLXI_3_XLXN_49, I1 => XLXI_3_XLXN_38, I2 => XLXI_3_XLXN_40, I3 => XLXI_3_XLXN_137, O => XLXI_3_XLXN_141 ); XLXI_3_XLXI_55 : X_AND4 port map ( I0 => XLXI_3_XLXN_40, I1 => XLXI_3_XLXN_39, I2 => XLXI_3_XLXN_49, I3 => XLXI_3_XLXN_48, ); XLXI_3_XLXI_23 : X_AND2 port map ( I0 => XLXI_3_XLXN_466, I1 => XLXI_3_XLXN_465, O => XLXI_3_XLXN_578 ); XLXI_3_XLXI_14 : X_AND2 port map ( I0 => XLXI_3_XLXN_453, I1 => XLXI_3_XLXN_452, O => href_OBUF_13 ); XLXI_3_XLXI_12 : X_INV port map ( I => XLXI_3_CLK, O => XLXI_3_XLXN_87 ); XLXI_3_XLXI_4 : X_OR5 port map ( I0 => XLXI_3_XLXN_48, I1 => XLXI_3_XLXN_12, I2 => XLXI_3_XLXN_11, I3 => XLXI_3_XLXN_10, I4 => XLXI_3_XLXN_51, O => NlwInverterSignal_XLXI_3_XLXI_4_O ); XLXI_3_XLXI_2 : X_OR5 port map ( I0 => XLXI_3_XLXN_137, I1 => XLXI_3_XLXN_40, I2 => XLXI_3_XLXN_39, I3 => XLXI_3_XLXN_38, I4 => XLXI_3_XLXN_49, O => NlwInverterSignal_XLXI_3_XLXI_2_O ); XLXI_3_XLXI_247 : X_FF generic map( INIT => '0' ) port map ( CLK => vref_OBUF_14, RST => XLXI_3_XLXN_595, I => N3, O => XLXI_3_XLXN_600, CE => VCC, SET => GND ); XLXI_3_XLXI_241 : X_FF generic map( INIT => '0' ) port map ( CLK => clk_40_BUFGP, I => N3, O => XLXI_3_XLXN_478, CE => VCC, SET => GND, RST => GND ); XLXI_3_XLXI_8 : X_FF generic map( INIT => '0' ) port map ( CLK => XLXN_91, I => XLXI_3_XLXN_87, O => XLXI_3_CLK, CE => VCC, SET => GND, RST => GND ); wr_en_IBUF : X_BUF port map ( I => wr_en, O => wr_en_IBUF_12 ); din_64_63_IBUF : X_BUF port map ( I => din_64(63), O => din_64_63_IBUF_25 ); din_64_62_IBUF : X_BUF port map ( I => din_64(62), O => din_64_62_IBUF_26 ); din_64_61_IBUF : X_BUF port map ( I => din_64(61), O => din_64_61_IBUF_27 ); din_64_60_IBUF : X_BUF port map ( I => din_64(60), O => din_64_60_IBUF_28 ); din_64_59_IBUF : X_BUF port map ( I => din_64(59), O => din_64_59_IBUF_29 ); din_64_58_IBUF : X_BUF port map ( I => din_64(58), O => din_64_58_IBUF_30 ); din_64_57_IBUF : X_BUF port map ( I => din_64(57), O => din_64_57_IBUF_31 ); din_64_56_IBUF : X_BUF port map ( I => din_64(56), O => din_64_56_IBUF_32 ); din_64_55_IBUF : X_BUF port map ( I => din_64(55), O => din_64_55_IBUF_33 ); din_64_54_IBUF : X_BUF port map ( I => din_64(54), O => din_64_54_IBUF_34 ); din_64_53_IBUF : X_BUF port map ( I => din_64(53), O => din_64_53_IBUF_35 ); din_64_52_IBUF : X_BUF port map ( I => din_64(52), O => din_64_52_IBUF_36 ); din_64_51_IBUF : X_BUF port map ( I => din_64(51), O => din_64_51_IBUF_37 ); din_64_50_IBUF : X_BUF port map ( I => din_64(50), O => din_64_50_IBUF_38 ); din_64_49_IBUF : X_BUF port map ( I => din_64(49), O => din_64_49_IBUF_39 ); din_64_48_IBUF : X_BUF port map ( I => din_64(48), O => din_64_48_IBUF_40 ); din_64_47_IBUF : X_BUF port map ( I => din_64(47), O => din_64_47_IBUF_41 ); din_64_46_IBUF : X_BUF port map ( I => din_64(46), O => din_64_46_IBUF_42 ); din_64_45_IBUF : X_BUF port map ( I => din_64(45), O => din_64_45_IBUF_43 ); din_64_44_IBUF : X_BUF port map ( I => din_64(44), O => din_64_44_IBUF_44 ); din_64_43_IBUF : X_BUF port map ( I => din_64(43), O => din_64_43_IBUF_45 ); din_64_42_IBUF : X_BUF port map ( I => din_64(42), O => din_64_42_IBUF_46 ); din_64_41_IBUF : X_BUF port map ( I => din_64(41), O => din_64_41_IBUF_47 ); din_64_40_IBUF : X_BUF port map ( I => din_64(40), O => din_64_40_IBUF_48 ); din_64_39_IBUF : X_BUF port map ( I => din_64(39), O => din_64_39_IBUF_49 ); din_64_38_IBUF : X_BUF port map ( I => din_64(38), O => din_64_38_IBUF_50?? 快捷鍵說明
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