?? sjall_translate.vhd
字號:
); din_64_37_IBUF : X_BUF port map ( I => din_64(37), O => din_64_37_IBUF_51 ); din_64_36_IBUF : X_BUF port map ( I => din_64(36), O => din_64_36_IBUF_52 ); din_64_35_IBUF : X_BUF port map ( I => din_64(35), O => din_64_35_IBUF_53 ); din_64_34_IBUF : X_BUF port map ( I => din_64(34), O => din_64_34_IBUF_54 ); din_64_33_IBUF : X_BUF port map ( I => din_64(33), O => din_64_33_IBUF_55 ); din_64_32_IBUF : X_BUF port map ( I => din_64(32), O => din_64_32_IBUF_56 ); din_64_31_IBUF : X_BUF port map ( I => din_64(31), O => din_64_31_IBUF_57 ); din_64_30_IBUF : X_BUF port map ( I => din_64(30), O => din_64_30_IBUF_58 ); din_64_29_IBUF : X_BUF port map ( I => din_64(29), O => din_64_29_IBUF_59 ); din_64_28_IBUF : X_BUF port map ( I => din_64(28), O => din_64_28_IBUF_60 ); din_64_27_IBUF : X_BUF port map ( I => din_64(27), O => din_64_27_IBUF_61 ); din_64_26_IBUF : X_BUF port map ( I => din_64(26), O => din_64_26_IBUF_62 ); din_64_25_IBUF : X_BUF port map ( I => din_64(25), O => din_64_25_IBUF_63 ); din_64_24_IBUF : X_BUF port map ( I => din_64(24), O => din_64_24_IBUF_64 ); din_64_23_IBUF : X_BUF port map ( I => din_64(23), O => din_64_23_IBUF_65 ); din_64_22_IBUF : X_BUF port map ( I => din_64(22), O => din_64_22_IBUF_66 ); din_64_21_IBUF : X_BUF port map ( I => din_64(21), O => din_64_21_IBUF_67 ); din_64_20_IBUF : X_BUF port map ( I => din_64(20), O => din_64_20_IBUF_68 ); din_64_19_IBUF : X_BUF port map ( I => din_64(19), O => din_64_19_IBUF_69 ); din_64_18_IBUF : X_BUF port map ( I => din_64(18), O => din_64_18_IBUF_70 ); din_64_17_IBUF : X_BUF port map ( I => din_64(17), O => din_64_17_IBUF_71 ); din_64_16_IBUF : X_BUF port map ( I => din_64(16), O => din_64_16_IBUF_72 ); din_64_15_IBUF : X_BUF port map ( I => din_64(15), O => din_64_15_IBUF_73 ); din_64_14_IBUF : X_BUF port map ( I => din_64(14), O => din_64_14_IBUF_74 ); din_64_13_IBUF : X_BUF port map ( I => din_64(13), O => din_64_13_IBUF_75 ); din_64_12_IBUF : X_BUF port map ( I => din_64(12), O => din_64_12_IBUF_76 ); din_64_11_IBUF : X_BUF port map ( I => din_64(11), O => din_64_11_IBUF_77 ); din_64_10_IBUF : X_BUF port map ( I => din_64(10), O => din_64_10_IBUF_78 ); din_64_9_IBUF : X_BUF port map ( I => din_64(9), O => din_64_9_IBUF_79 ); din_64_8_IBUF : X_BUF port map ( I => din_64(8), O => din_64_8_IBUF_80 ); din_64_7_IBUF : X_BUF port map ( I => din_64(7), O => din_64_7_IBUF_81 ); din_64_6_IBUF : X_BUF port map ( I => din_64(6), O => din_64_6_IBUF_82 ); din_64_5_IBUF : X_BUF port map ( I => din_64(5), O => din_64_5_IBUF_83 ); din_64_4_IBUF : X_BUF port map ( I => din_64(4), O => din_64_4_IBUF_84 ); din_64_3_IBUF : X_BUF port map ( I => din_64(3), O => din_64_3_IBUF_85 ); din_64_2_IBUF : X_BUF port map ( I => din_64(2), O => din_64_2_IBUF_86 ); din_64_1_IBUF : X_BUF port map ( I => din_64(1), O => din_64_1_IBUF_87 ); din_64_0_IBUF : X_BUF port map ( I => din_64(0), O => din_64_0_IBUF_88 ); XLXI_3_XLXI_1_XST_GND : X_ZERO port map ( O => XLXI_3_XLXI_1_N0 ); XLXI_3_XLXI_1_I_36_67 : X_AND2 port map ( I0 => XLXI_3_XLXN_2, I1 => XLXI_3_XLXI_1_TC, O => XLXI_3_XLXI_1_CEO ); XLXI_3_XLXI_1_I_36_58 : X_ONE port map ( O => XLXI_3_XLXI_1_XLXN_1 ); XLXI_3_XLXI_1_I_36_33 : X_AND2 port map ( I0 => XLXI_3_XLXN_137, I1 => XLXI_3_XLXN_40, O => XLXI_3_XLXI_1_T2 ); XLXI_3_XLXI_1_I_36_32 : X_AND3 port map ( I0 => XLXI_3_XLXI_1_Q2, I1 => XLXI_3_XLXN_137, I2 => XLXI_3_XLXN_40, O => XLXI_3_XLXI_1_T3 ); XLXI_3_XLXI_1_I_36_31 : X_AND4 port map ( I0 => XLXI_3_XLXI_1_Q3, I1 => XLXI_3_XLXI_1_Q2, I2 => XLXI_3_XLXN_137, I3 => XLXI_3_XLXN_40, O => XLXI_3_XLXI_1_TC ); XLXI_3_XLXI_1_I_Q3_XST_VCC : X_ONE port map ( O => XLXI_3_XLXI_1_I_Q3_N1 ); XLXI_3_XLXI_1_I_Q3_XST_GND : X_ZERO port map ( O => XLXI_3_XLXI_1_I_Q3_N0 ); XLXI_3_XLXI_1_I_Q3_I_36_32 : X_XOR2 port map ( I0 => XLXI_3_XLXI_1_T3, I1 => XLXI_3_XLXI_1_Q3, O => XLXI_3_XLXI_1_I_Q3_TQ ); XLXI_3_XLXI_1_I_Q3_I_36_35 : X_FF generic map( INIT => '0' ) port map ( CLK => XLXI_3_CLK, CE => XLXI_3_XLXN_2, RST => XLXI_3_XLXN_260, I => XLXI_3_XLXI_1_I_Q3_TQ, O => XLXI_3_XLXI_1_Q3, SET => GND ); XLXI_3_XLXI_1_I_Q2_XST_VCC : X_ONE port map ( O => XLXI_3_XLXI_1_I_Q2_N1 ); XLXI_3_XLXI_1_I_Q2_XST_GND : X_ZERO port map ( O => XLXI_3_XLXI_1_I_Q2_N0 ); XLXI_3_XLXI_1_I_Q2_I_36_32 : X_XOR2 port map ( I0 => XLXI_3_XLXI_1_T2, I1 => XLXI_3_XLXI_1_Q2, O => XLXI_3_XLXI_1_I_Q2_TQ ); XLXI_3_XLXI_1_I_Q2_I_36_35 : X_FF generic map( INIT => '0' ) port map ( CLK => XLXI_3_CLK, CE => XLXI_3_XLXN_2, RST => XLXI_3_XLXN_260, I => XLXI_3_XLXI_1_I_Q2_TQ, O => XLXI_3_XLXI_1_Q2, SET => GND ); XLXI_3_XLXI_1_I_Q1_XST_VCC : X_ONE port map ( O => XLXI_3_XLXI_1_I_Q1_N1 ); XLXI_3_XLXI_1_I_Q1_XST_GND : X_ZERO port map ( O => XLXI_3_XLXI_1_I_Q1_N0 ); XLXI_3_XLXI_1_I_Q1_I_36_32 : X_XOR2 port map ( I0 => XLXI_3_XLXN_40, I1 => XLXI_3_XLXN_137, O => XLXI_3_XLXI_1_I_Q1_TQ ); XLXI_3_XLXI_1_I_Q1_I_36_35 : X_FF generic map( INIT => '0' ) port map ( CLK => XLXI_3_CLK, CE => XLXI_3_XLXN_2, RST => XLXI_3_XLXN_260, I => XLXI_3_XLXI_1_I_Q1_TQ, O => XLXI_3_XLXN_137, SET => GND ); XLXI_3_XLXI_1_I_Q0_XST_VCC : X_ONE port map ( O => XLXI_3_XLXI_1_I_Q0_N1 ); XLXI_3_XLXI_1_I_Q0_XST_GND : X_ZERO port map ( O => XLXI_3_XLXI_1_I_Q0_N0 ); XLXI_3_XLXI_1_I_Q0_I_36_32 : X_XOR2 port map ( I0 => XLXI_3_XLXI_1_XLXN_1, I1 => XLXI_3_XLXN_40, O => XLXI_3_XLXI_1_I_Q0_TQ ); XLXI_3_XLXI_1_I_Q0_I_36_35 : X_FF generic map( INIT => '0' ) port map ( CLK => XLXI_3_CLK, CE => XLXI_3_XLXN_2, RST => XLXI_3_XLXN_260, I => XLXI_3_XLXI_1_I_Q0_TQ, O => XLXI_3_XLXN_40, SET => GND ); XLXI_3_XLXI_3_XST_GND : X_ZERO port map ( O => XLXI_3_XLXI_3_N0 ); XLXI_3_XLXI_3_I_36_67 : X_AND2 port map ( I0 => XLXI_3_XLXN_4, I1 => XLXI_3_XLXN_2, O => XLXI_3_XLXI_3_CEO ); XLXI_3_XLXI_3_I_36_58 : X_ONE port map ( O => XLXI_3_XLXI_3_XLXN_1 ); XLXI_3_XLXI_3_I_36_33 : X_AND2 port map ( I1 => XLXI_3_XLXN_48, O => XLXI_3_XLXI_3_T2 ); XLXI_3_XLXI_3_I_36_32 : X_AND3 port map ( I0 => XLXI_3_XLXN_38,?? 快捷鍵說明
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