signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_10_FFY_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_FFX_SET : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_FFX_SET : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_10_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_FFX_RST : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_FFX_RST : STD_LOGIC;   signal GND : STD_LOGIC;   signal VCC : STD_LOGIC;   signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR : STD_LOGIC_VECTOR ( 10 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR : STD_LOGIC_VECTOR ( 7 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r : STD_LOGIC_VECTOR ( 10 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_r : STD_LOGIC_VECTOR ( 7 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w : STD_LOGIC_VECTOR ( 7 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w : STD_LOGIC_VECTOR ( 7 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_debug_rd_pntr_w : STD_LOGIC_VECTOR ( 10 downto 3 );   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2 : STD_LOGIC_VECTOR ( 10 downto 3 );   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc : STD_LOGIC_VECTOR ( 7 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2 : STD_LOGIC_VECTOR ( 7 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc : STD_LOGIC_VECTOR ( 10 downto 3 );   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x : STD_LOGIC_VECTOR ( 7 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x : STD_LOGIC_VECTOR ( 10 downto 3 );   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 7 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 7 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1 : STD_LOGIC_VECTOR ( 5 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1 : STD_LOGIC_VECTOR ( 5 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 7 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 10 downto 0 );   signal XLXI_2_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 10 downto 0 ); begin  XLXN_94 <= NlwRenamedSig_OI_XLXN_94;  XLXI_3_XLXN_48_BYMUX : X_INV    generic map(      LOC => "CLB_R16C9.S0"    )    port map (      I => XLXI_3_XLXN_48,      O => XLXI_3_XLXN_48_BYMUXNOT    );  XLXI_3_XLXI_3_I_Q0_I_36_35 : X_FF    generic map(      LOC => "CLB_R16C9.S0",      INIT => '0'    )    port map (      I => XLXI_3_XLXN_48_BYMUXNOT,      CE => XLXI_3_XLXN_4_0,      CLK => XLXI_3_CLK,      SET => GND,      RST => XLXI_3_XLXN_48_FFY_RST,      O => XLXI_3_XLXN_48    );  XLXI_3_XLXN_48_FFY_RSTOR : X_BUF    generic map(      LOC => "CLB_R16C9.S0"    )    port map (      I => XLXI_3_XLXN_260_0,      O => XLXI_3_XLXN_48_FFY_RST    );  din_64_17_IMUX : X_BUF    generic map(      LOC => "PAD24"    )    port map (      I => din_64_17_IBUF_11,      O => din_64_17_IBUF_0    );  din_64_17_IBUF : X_BUF    generic map(      LOC => "PAD24"    )    port map (      I => din_64(17),      O => din_64_17_IBUF_11    );  din_64_25_IMUX : X_BUF    generic map(      LOC => "PAD39"    )    port map (      I => din_64_25_IBUF_12,      O => din_64_25_IBUF_0    );  din_64_25_IBUF : X_BUF    generic map(      LOC => "PAD39"    )    port map (      I => din_64(25),      O => din_64_25_IBUF_12    );  din_64_33_IMUX : X_BUF    generic map(      LOC => "PAD58"    )    port map (      I => din_64_33_IBUF_13,      O => din_64_33_IBUF_0    );  din_64_33_IBUF : X_BUF    generic map(      LOC => "PAD58"    )    port map (      I => din_64(33),      O => din_64_33_IBUF_13    );  din_64_41_IMUX : X_BUF    generic map(      LOC => "PAD86"    )    port map (      I => din_64_41_IBUF_14,      O => din_64_41_IBUF_0    );  din_64_41_IBUF : X_BUF    generic map(      LOC => "PAD86"    )    port map (      I => din_64(41),      O => din_64_41_IBUF_14    );  din_64_18_IMUX : X_BUF    generic map(      LOC => "PAD25"    )    port map (      I => din_64_18_IBUF_15,      O => din_64_18_IBUF_0    );  din_64_18_IBUF : X_BUF    generic map(      LOC => "PAD25"    )    port map (      I => din_64(18),      O => din_64_18_IBUF_15    );  din_64_26_IMUX : X_BUF    generic map(      LOC => "PAD42"    )    port map (      I => din_64_26_IBUF_16,      O => din_64_26_IBUF_0    );  din_64_26_IBUF : X_BUF    generic map(      LOC => "PAD42"    )    port map (      I => din_64(26),      O => din_64_26_IBUF_16    );  din_64_34_IMUX : X_BUF    generic map(      LOC => "PAD59"    )    port map (      I => din_64_34_IBUF_17,      O => din_64_34_IBUF_0    );  din_64_34_IBUF : X_BUF    generic map(      LOC => "PAD59"    )    port map (      I => din_64(34),      O => din_64_34_IBUF_17    );  din_64_42_IMUX : X_BUF    generic map(      LOC => "PAD87"    )    port map (      I => din_64_42_IBUF_18,      O => din_64_42_IBUF_0    );  din_64_42_IBUF : X_BUF    generic map(      LOC => "PAD87"    )    port map (      I => din_64(42),      O => din_64_42_IBUF_18    );  din_64_50_IMUX : X_BUF    generic map(      LOC => "PAD106"    )    port map (      I => din_64_50_IBUF_19,      O => din_64_50_IBUF_0    );  din_64_50_IBUF : X_BUF    generic map(      LOC => "PAD106"    )    port map (      I => din_64(50),      O => din_64_50_IBUF_19    );  din_64_19_IMUX : X_BUF    generic map(      LOC => "PAD27"    )    port map (      I => din_64_19_IBUF_20,      O => din_64_19_IBUF_0    );  din_64_19_IBUF : X_BUF    generic map(      LOC => "PAD27"    )    port map (      I => din_64(19),      O => din_64_19_IBUF_20    );  din_64_27_IMUX : X_BUF    generic map(      LOC => "PAD45"    )    port map (      I => din_64_27_IBUF_21,      O => din_64_27_IBUF_0    );  din_64_27_IBUF : X_BUF    generic map(      LOC => "PAD45"    )    port map (      I => din_64(27),      O => din_64_27_IBUF_21    );  din_64_35_IMUX : X_BUF