?? njhk_8_8.mdl
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PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
Interpolate on
}
Block {
BlockType Lookup
InputValues "[-4:5]"
OutputValues " rand(1,10)-0.5"
LookUpMeth "Interpolation-Extrapolation"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
LUTDesignTableMode "Redesign Table"
LUTDesignDataSource "Block Dialog"
LUTDesignFunctionName "sqrt(x)"
LUTDesignUseExistingBP on
LUTDesignRelError "0.01"
LUTDesignAbsError "1e-6"
}
Block {
BlockType Memory
X0 "0"
InheritSampleTime off
LinearizeMemory off
StateMustResolveToSignalObject off
RTWStateStorageClass "Auto"
}
Block {
BlockType Outport
Port "1"
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType PMComponent
SubClassName "unknown"
}
Block {
BlockType PMIOPort
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Saturate
UpperLimit "0.5"
LowerLimit "-0.5"
LinearizeAsGain on
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Scope
Floating off
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "0"
}
Block {
BlockType "S-Function"
FunctionName "system"
PortCounts "[]"
SFunctionModules "''"
}
Block {
BlockType Sin
SineType "Time based"
TimeSource "Use simulation time"
Amplitude "1"
Bias "0"
Frequency "1"
Phase "0"
Samples "10"
Offset "0"
SampleTime "-1"
VectorParams1D on
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Terminator
}
Block {
BlockType ToWorkspace
VariableName "simulink_output"
MaxDataPoints "1000"
Decimation "1"
SampleTime "0"
FixptAsFi off
}
Block {
BlockType UnitDelay
X0 "0"
SampleTime "1"
StateMustResolveToSignalObject off
RTWStateStorageClass "Auto"
}
Block {
BlockType ZeroOrderHold
SampleTime "1"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "Njhk_8_8"
Location [2, 82, 1014, 721]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 212
ScreenColor "white"
PaperOrientation "rotated"
PaperPositionMode "auto"
PaperType "a4letter"
PaperUnits "centimeters"
ZoomFactor "98"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "220V\n50Hz"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [43, 190, 67, 225]
Orientation "up"
NamePlacement "alternate"
SourceBlock "powerlib/Electrical\nSources/AC Voltage Source"
SourceType "AC Voltage Source"
ShowPortLabels on
Amplitude "311"
Phase "0"
Frequency "50"
SampleTime "0"
Measurements "None"
}
Block {
BlockType Reference
Name "288.8ohm\n/500W"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [846, 200, 864, 260]
Orientation "down"
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
Resistance "288.8"
Inductance "0"
Capacitance "inf"
Measurements "None"
}
Block {
BlockType Reference
Name "940uF"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [811, 200, 839, 270]
Orientation "down"
NamePlacement "alternate"
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
Resistance "0"
Inductance "0"
Capacitance "0.94e-3"
Measurements "None"
}
Block {
BlockType Clock
Name "Clock"
Position [95, 369, 155, 401]
DisplayTime on
Decimation "20"
}
Block {
BlockType Reference
Name "Current Measurement"
Ports [0, 1, 0, 0, 0, 1, 1]
Position [485, 108, 510, 132]
ShowName off
SourceBlock "powerlib/Measurements/Current Measurement"
SourceType "Current Measurement"
ShowPortLabels on
PhasorSimulation off
OutputType "Complex"
PSBequivalent "0"
Port {
PortNumber 1
Name "I_L"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Reference
Name "Current Measurement1"
Ports [0, 1, 0, 0, 0, 1, 1]
Position [85, 103, 110, 127]
ShowName off
SourceBlock "powerlib/Measurements/Current Measurement"
SourceType "Current Measurement"
ShowPortLabels on
PhasorSimulation off
OutputType "Complex"
PSBequivalent "0"
Port {
PortNumber 1
Name "Iac"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Reference
Name "Current Measurement2"
Ports [0, 1, 0, 0, 0, 1, 1]
Position [770, 123, 795, 147]
ShowName off
SourceBlock "powerlib/Measurements/Current Measurement"
SourceType "Current Measurement"
ShowPortLabels on
PhasorSimulation off
OutputType "Complex"
PSBequivalent "0"
Port {
PortNumber 1
Name "I_Diode"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Reference
Name "Diode"
Ports [0, 1, 0, 0, 0, 1, 1]
Position [645, 105, 700, 145]
SourceBlock "powerlib/Power\nElectronics/Diode"
SourceType "Diode"
ShowPortLabels on
Ron "0.001"
Lon "0"
Vf "0.8"
IC "0"
Rs "500"
Cs "250e-9"
Measurements on
}
Block {
BlockType Reference
Name "Diode1"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [181, 140, 209, 180]
Orientation "up"
AttributesFormatString "\\n"
SourceBlock "powerlib/Power\nElectronics/Diode"
SourceType "Diode"
ShowPortLabels on
Ron "0.01"
Lon "0"
Vf "0.8"
IC "0"
Rs "250"
Cs "0.1e-6"
Measurements off
}
Block {
BlockType Reference
Name "Diode2"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [181, 240, 209, 280]
Orientation "up"
AttributesFormatString "\\n"
SourceBlock "powerlib/Power\nElectronics/Diode"
SourceType "Diode"
ShowPortLabels on
Ron "0.01"
Lon "0"
Vf "0.8"
IC "0"
Rs "250"
Cs "0.1e-6"
Measurements off
}
Block {
BlockType Reference
Name "Diode3"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [241, 140, 269, 180]
Orientation "up"
AttributesFormatString "\\n"
SourceBlock "powerlib/Power\nElectronics/Diode"
SourceType "Diode"
ShowPortLabels on
Ron "0.01"
Lon "0"
Vf "0.8"
IC "0"
Rs "250"
Cs "0.1e-6"
Measurements off
}
Block {
BlockType Reference
Name "Diode4"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [241, 240, 269, 280]
Orientation "up"
AttributesFormatString "\\n"
SourceBlock "powerlib/Power\nElectronics/Diode"
SourceType "Diode"
ShowPortLabels on
Ron "0.01"
Lon "0"
Vf "0.8"
IC "0"
Rs "250"
Cs "0.1e-6"
Measurements off
}
Block {
BlockType Gain
Name "Gain_IL"
Position [595, 240, 625, 275]
Orientation "down"
Gain "0.3"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain_Vin"
Position [343, 370, 387, 415]
Orientation "down"
NamePlacement "alternate"
Gain "1/450"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain_Vout"
Position [937, 285, 983, 325]
Orientation "down"
NamePlacement "alternate"
Gain "1/450"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Ground1"
Ports [0, 0, 0, 0, 0, 1]
Position [299, 340, 321, 365]
Orientation "down"
ShowName off
SourceBlock "powerlib/Elements/Ground"
SourceType "Ground"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "a"
}
Block {
BlockType Reference
Name "Ground2"
Ports [0, 0, 0, 0, 0, 1]
Position [559, 280, 581, 305]
Orientation "down"
ShowName off
SourceBlock "powerlib/Elements/Ground"
SourceType "Ground"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "a"
}
Block {
BlockType Reference
Name "Ground3"
Ports [0, 0, 0, 0, 0, 1]
Position [869, 180, 891, 205]
Orientation "down"
ShowName off
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