;**********************************************************************
;															          ;
; 	        HT46R47 Demo Board for Single phase BLDC Motor            ;
;															          ;
; System Clock: 2MHz												  ;
; PWM frequency: 31KHz  											  ;
;**********************************************************************
INCLUDE	HT46R47.INC	

DATA			.SECTION	AT 40H	'DATA'
;-------------------------------------------------
maincon			db		?
temp0			db		?
temp1			db		?
hdata			db		?
otimer0			db		?
otimer1			db		?

;---------- AD convert  --------------------------
adcount			db		?
adcon			db		?
adstatus		db		?
speedh			db		?
speedl			db		?
adc_buff		db		?

adata_ch0		db		?
adata_ch1		db		?
adata_ch2		db		?
adata_ch3		db		?
;-------------------------------------------------

;*****************************************************************
CODE			.SECTION	

				org 	00H

 				jmp		initial

				org		04H
				jmp		extint_sub

				org		08H
				jmp		timerint_sub

;--------------------------------------------------
				ORG		020H	

initial:									; Clear all data ram from 40H to 7FH
				mov		a,40H
				mov		mp0,a
				jmp		clramloop

clramloop:									 
				clr		r0
				
				mov		a,0feH
				sub		a,mp0
				sz		status.2		
				jmp		ini_specram

				inc		mp0		
				jmp		clramloop			; If MP0 is equal to the data "FEH", jump to clramloop; MP0 < 3FH	

;--------------------------------------------------	
ini_specram:			
				mov		a,00100011b			;  	
				mov		PAC,a
		
				mov		a,00000100b			; bit6:Q7=off,Q3+off;  bit7:Q8=off,Q4=off, PA.2 led off 
				mov		PA,a

				mov		a,00001111b			;  	
				mov		PBC,a
		
				mov		a,00001111b
				mov		PB,a

				mov		a,00h				;  	
				mov		PDC,a
		
				mov		a,00h
				mov		PD,a
;.....................................
				mov		a,10000010b			; timer mode, prescaler=fsys/4, timer off
				mov		tmrc,a

				mov		a,132d				; 250us  
				mov		tmr,a

				mov		a,00000110b			; ADC int disable, TMR/EXT int enable  
				mov		intc,a

				mov		a,00000001b			; AD converter clock source, fsys/8 
				mov		acsr,a		

				mov		a,00010000b			; pb0 ~ pb2 are all enabled as ADC inputs 
				mov		adcr,a				

				mov		a,01d
				mov		pwm,a

				set		intc.0				; global int enable 
				set		tmrc.4				; timer on

;----------------------------------------------------------------------------
;
;    		--	 MAIN PROGRAM LOOP  --  
;
;----------------------------------------------------------------------------
main_loop:
				clr		wdt
    			sz		maincon.7			;  
				jmp		main_loop			; over time 
        
    			snz		maincon.0			;  
				jmp		main_loop			; 

				clr		maincon.0

				snz		maincon.1			;
				jmp		adc_loop			; 
			 	jmp		hall_loop			; 


;------------------------------------------------------------------------
;  			-- ADC control loop -- 500us
;------------------------------------------------------------------------
adc_loop:
				sz		adstatus.0			;     
				jmp		ad_convert

				mov		a,offset adata_ch0
				mov		mp0,a

adc_start:
				clr		adcr.7				; strat ad convert
				set		adcr.7
				clr		adcr.7	
				set		adstatus.0

ad_convert:
				sz		adcr.6
				jmp		ad_back

				clr		adstatus.0

				mov		a,adrh
				mov		speedh,a

				mov		a,adrl
				mov		speedl,a	

				mov		a,r0
				addm	a,speedh
				rrc		speedh
				mov		a,speedh
				mov		r0,a
		
				inc		mp0							
				inc		adcr				; channel 0~2
				snz		adcr.1				; 
				jmp		adc_start
				snz		adcr.0
				jmp		adc_start
				
				clr		adcr.0				; reset ad to channel 0
				clr		adcr.1
			
				inc		adcount				; ad convert times 
				mov		a,04H
				sub		a,adcount
				sz		status.2
				jmp		end_adc_loop
				jmp		ad_back
				
end_adc_loop:			
				set		adstatus.1			; ad convert finished	

ad_back:
				set		maincon.1			; hall loop
				jmp		main_loop	

;-----------------------------------------------------------------------
; 			-- HALL and Timer loop -- 500us
;-----------------------------------------------------------------------
hall_loop:
				sz		maincon.3			; 
				jmp		timer_loop			; BLDC motor is running

				sz		maincon.2			
				jmp		fpwm_loop			; first run is set

				snz		adstatus.1			; ad converted ok?
				jmp		hall_loop_back

				clr		adstatus.1	

first_run:
				sz		pa.4				; I/O for INT, if pa.4 is low, hall output is inverted  
				jmp		intio_hi			; hall IC output status is uninverted
				jmp		intio_lo			; hall IC output status is inverted

intio_lo:
				sz		pa.5				; INT pin /hall status
				jmp		tfhall_lo			; hall IC output low 
				set		pa.4				; I/O for INT falling edge
				jmp		tfhall_hi			; hall IC output high

intio_hi:
				sz		pa.5				; INT pin /hall status
				jmp		tfhall_hi			; hall IC output high 
				clr		pa.4				; I/O for int falling edge
				jmp		tfhall_lo			; hall IC output low

tfhall_lo:

				clr		pd.0				; PWM off
				clr		pa.6				; Q3 off
				set		pa.7				; Q4 on

				call	fpwm_load

				set    	pd.0				; PWM enable
				set		maincon.2			; timer loop
				jmp		timer_loop

tfhall_hi:
				clr		pd.0				; PWM off
				clr		pa.7				; Q3 off
				set		pa.6				; Q4 on

				call	fpwm_load

				set    	pd.0				; PWM enable
				set		maincon.2           ; timer loop
				jmp		timer_loop

fpwm_loop:
				call	fpwm_load
				jmp		timer_loop

timer_loop:
				call	overtime_test
				jmp		hall_loop_back

hall_loop_back:
				clr		maincon.1
				jmp		main_loop

;-------------------------------------------------------------------------
overtime_test:	
			
				siz		otimer0
				jmp		ot_back
				inc		otimer1
				mov		a,10d				; 
				sub		a,otimer1
				sz		status.0
				jmp		ot_back
				jmp		ovrun

ovrun:
				clr		pd.0
				clr		pa.6
				clr		pa.7

				clr		maincon
				set		maincon.7			; set over run	
				clr		pa.2				; over run led on
				clr		intc.0				; INT disable
				clr		adstatus
				clr		tmrc.4

ot_back:
				ret
;--------------------------------------------------------------------------
; first_run: the pwm value increment from low value to high value  
;--------------------------------------------------------------------------
fpwm_load:

				inc		pwm
				mov		a,168d				; 
				sub		a,pwm
				sz		status.0
				ret

				mov		a,01d				; fpwm data = 01d, load the pwm initialzation value
				mov		pwm,a		
				ret
;----------------------------------------------------------------------------
;    		--	 PWM_OUT_TEST SUB PROGRAM   -- 
;----------------------------------------------------------------------------
pwm_load:
				sz		pa.1
				jmp		pwm_in
				sz		pa.0
				jmp		ntc_in
				jmp		vr_in
pwm_in:
				mov		a,adata_ch2
				mov		pwm,a
				jmp		psub_back
ntc_in:
				mov		a,adata_ch1
				mov		pwm,a
				jmp		psub_back
vr_in:
				mov		a,adata_ch0
				mov		pwm,a
				jmp		psub_back

psub_back:
				ret


;----------------------------------------------------------------------------
;    		--	 EXT0INT SUB   --
;----------------------------------------------------------------------------
extint_sub:
				mov		temp0,a
				mov		a,status
				mov		temp1,a

				clr		intc.4

				sz		PA.4
				jmp		hall_change2lo		; the prevrious hall output data is high 
				jmp		hall_change2hi		; the prevrious hall output data is low 

hall_change2hi:
				set		pA.4				; I/O for int switchihg
	
				clr		PD.0				; stop the PWM output
				clr		PA.6				
				set		PA.7
			 
				call	pwm_load
				set		pd.0
				jmp		ext_back

hall_change2lo:

				clr		pa.4				; I/O for int switching

				clr		pd.0				; stop the PWM output 
				clr		PA.7				 
				set		pA.6				

				call	pwm_load
				set		pd.0
sig_out:
				mov		a,00001000b
				xorm	a,pa

				jmp		ext_back

ext_back:
				clr		otimer0
				clr		otimer1

				set		maincon.3			; DLDC motor is running 


				mov		a,temp1
				mov		status,a
				mov		a,temp0
  
				reti

;----------------------------------------------------------------------------
;    		--	 TIMER0INT SUB   --
;----------------------------------------------------------------------------
timerint_sub:
;				mov		temp0,a
;				mov		a,status
;				mov		temp1,a

				set		maincon.0

;				mov		a,temp1
;				mov		status,a
;				mov		a,temp0
  
				reti
	
;----------------------------------------------------------------------------
				end