return;
}

#if 0
BOOL IIC_WriteByte(unsigned short uAddr, unsigned char ucData)
{
    int i,delay = 0;
    int iStatus;
    unsigned long dwLoop1,dwLoop2;

    if( v_pIICReg == NULL )
    {
        return FALSE;
    }
    
    /* output salve device address */
    v_pIICReg->rIICDS   = SLAVE_IIC_ADDR;
    v_pIICReg->rIICSTAT = 0xf0;

    /* output address */
    v_pIICReg->rIICDS  = uAddr;
    for( i = 0; i < 10; i++);
    {
        delay++;
    }
    v_pIICReg->rIICCON = 0xe0;     //resumes IIC operation

    /* output data */
    v_pIICReg->rIICDS  = ucData;
    for( i = 0; i < 10; i++);
    {
        delay++;
    }
    v_pIICReg->rIICCON = 0xe0;     //resumes IIC operation
    
    /* stop */
    v_pIICReg->rIICSTAT = 0xd0;                //stop MasTx condition 
    v_pIICReg->rIICCON  = 0xe0;                //resumes IIC operation.
    Delay(1);                       //wait until stop condtion is in effect.

    /* confire ack */
    dwLoop2 = 0;
    while( TRUE )
    {
        v_pIICReg->rIICDS     = SLAVE_IIC_ADDR;
        iStatus               = 0x100;             //To check if _iicStatus is changed 
        v_pIICReg->rIICSTAT   = 0xf0;              //Master Tx, Start, Output Enable, Sucessful, Cleared, Cleared, 0
        v_pIICReg->rIICCON    = 0xe0;              //Resumes IIC operation. //hzh

        dwLoop1 = 0;
        while( (iStatus == 0x100) )
        {
            iStatus = v_pIICReg->rIICSTAT;
            dwLoop1++;
            if( dwLoop1 >= 32 )
            {
                return FALSE;
            }
        }

        if( !(iStatus & 0x1) )
            break;                      //When ACK is received

        dwLoop2++;
        if( dwLoop2 >= 3)
        {
            return FALSE;
        }
    }
    v_pIICReg->rIICSTAT = 0xd0;             //Master Tx condition, Stop(Write), Output Enable
    v_pIICReg->rIICCON  = 0xe0;             //Resumes IIC operation.
    Delay(1);        

    return TRUE;
    
}

BOOL IIC_ReadByte(unsigned short uAddr, unsigned char* pucData )
{
    int				i,delay = 0;
    unsigned char   aucData[4] = {0};
    
    if( v_pIICReg == NULL || pucData == NULL )
    {
        return FALSE;
    }

    /* output salve device address */
    v_pIICReg->rIICDS   = SLAVE_IIC_ADDR;
    v_pIICReg->rIICSTAT = 0xf0;                    //MasTx,Start // read cmd = 0xa1, write = 0xa0

    /* output address */
    v_pIICReg->rIICDS = uAddr;
    for( i = 0; i < 10; i++ )          //for setup time until rising edge of IICSCL
    {
        delay++;
    }
    v_pIICReg->rIICCON = 0xe0;          //resumes IIC operation.

                
    /* output salve address and stop */    
    v_pIICReg->rIICDS   = SLAVE_IIC_ADDR;
    v_pIICReg->rIICSTAT = 0xb0;                    //Master Rx,Start
    v_pIICReg->rIICCON  = 0xe0;                    //Resumes IIC operation.

    aucData[0] = v_pIICReg->rIICDS;
    //The last data has to be read with no ack.
    v_pIICReg->rIICCON = 0x60;                  //Resumes IIC operation with NOACK.
    
    aucData[1] = v_pIICReg->rIICDS;
    v_pIICReg->rIICSTAT = 0x90;                 //Stop MasRx condition 
    v_pIICReg->rIICCON  = 0xe0;                 //Resumes IIC operation.
    Delay(1);                       //Wait until stop condtion is in effect.
    //Too long time... 
    //The pending bit will not be set after issuing stop condition.
    *pucData = aucData[1];
    return TRUE;
}
#endif

#if 0
//*************************[ Wr24C080 ]****************************
BOOL IIC_WriteByte(unsigned short uAddr, unsigned char ucData)
{
    int iLoop1 = 0,iLoop2 = 0;
    
    g_dwI2CMode     = EN_I2C_WRDATA;
    g_ucI2CPt       = 0;
    g_ucI2CBuff[0]  = (unsigned char)uAddr;
    g_ucI2CBuff[1]  = ucData;
    g_iI2CDataCount = 2;
    
    v_pIICReg->rIICDS   = SLAVE_IIC_ADDR;           //0xa0
    v_pIICReg->rIICSTAT = 0xf0;                     //MasTx,Start
      //Clearing the pending bit isn't needed because the pending bit has been cleared.

    iLoop1 = 0;
    while( g_iI2CDataCount!=-1 )
    {
        iLoop1++;
        if( iLoop1 >= I2C_WAIT_INT_MAX_COUNT )
        {
            v_pIICReg->rIICSTAT = 0xd0;             //Stop MasTx condition 
            v_pIICReg->rIICCON  = 0xe0;             //Resumes IIC operation.
            return (FALSE);
        }
        Sleep(5);
    }

    g_dwI2CMode = EN_I2C_POLLACK;

    iLoop1 = 0;
    while( TRUE )
    {
        v_pIICReg->rIICDS   = SLAVE_IIC_ADDR;
        g_iI2CStatus        = 0x100;
        v_pIICReg->rIICSTAT = 0xf0;              //MasTx,Start
        v_pIICReg->rIICCON  = 0xe0;             //0xaf;  Resumes IIC operation.

        iLoop2 = 0;   
        while( g_iI2CStatus == 0x100 );
        {
            iLoop2++;
            if( iLoop2 >= I2C_WAIT_INT_MAX_COUNT )
            {
                v_pIICReg->rIICSTAT = 0xd0;             //Stop MasTx condition 
                v_pIICReg->rIICCON  = 0xe0;             //Resumes IIC operation.
                return (FALSE);
            }
            Sleep(5);
        }
           
        if( !(g_iI2CStatus & 0x1) )
            break;                      //When ACK is received

        iLoop1++;
        if( iLoop1 >= I2C_WAIT_INT_MAX_COUNT )
        {
            v_pIICReg->rIICSTAT = 0xd0;             //Stop MasTx condition 
            v_pIICReg->rIICCON  = 0xe0;             //Resumes IIC operation.
            return (FALSE);
        }
        Sleep(5);
        
    }
    v_pIICReg->rIICSTAT = 0xd0;             //Stop MasTx condition 
    v_pIICReg->rIICCON  = 0xe0;             //Resumes IIC operation.
    Delay(1);                               //Wait until stop condtion is in effect.
    //Write is completed.

    return (TRUE);
}
        
//**********************[ Rd24C080 ] ***********************************
BOOL IIC_ReadByte(unsigned short uAddr, unsigned char* pucData )
{
    int iLoop1 = 0,iLoop2 = 0;
    
    g_dwI2CMode     = EN_I2C_SETRDADDR;
    g_ucI2CPt       = 0;
    g_ucI2CBuff[0]  = (unsigned char)uAddr;    
    g_iI2CDataCount = 1;

    v_pIICReg->rIICDS   = SLAVE_IIC_ADDR;
    v_pIICReg->rIICSTAT = 0xf0;                    //MasTx,Start  
      //Clearing the pending bit isn't needed because the pending bit has been cleared.
    while( g_iI2CDataCount != -1 )
    {
        iLoop1++;
        if( iLoop1 >= I2C_WAIT_INT_MAX_COUNT )
        {
            RETAILMSG(1,(TEXT("IIC1 Read Byte failed!\r\n")));
            return (FALSE);
        }
        Sleep(5);
    }

    g_dwI2CMode     = EN_I2C_RDDATA;
    g_ucI2CPt       = 0;
    g_iI2CDataCount = 1;
    
    v_pIICReg->rIICDS   = SLAVE_IIC_ADDR;
    v_pIICReg->rIICSTAT = 0xb0;               //MasRx,Start
    v_pIICReg->rIICCON  = 0xe0;//0xaf;               //Resumes IIC operation.	//hzh
    while( g_iI2CDataCount != -1 )
    {
        iLoop2++;
        if( iLoop2 >= I2C_WAIT_INT_MAX_COUNT )
        {
            RETAILMSG(1,(TEXT("IIC2 Read Byte failed!\r\n")));
            return (FALSE);
        }
        Sleep(5);
    }
    *pucData = g_ucI2CBuff[1];
    return (TRUE);
}

#endif

//**********************[IicPoll ]**************************************
void IIC_Poll(void)
{
    unsigned long iicSt,i;

    if( !( v_pIICReg->rIICCON & 0x10 ) )
    {
        return;
    }
        
    iicSt = v_pIICReg->rIICSTAT; 
    if(iicSt & 0x8){}                   //When bus arbitration is failed.
    if(iicSt & 0x4){}                   //When a slave address is matched with IICADD
    if(iicSt & 0x2){}                   //When a slave address is 0000000b
    if(iicSt & 0x1){}                   //When ACK isn't received

    switch(g_dwI2CMode)
    {
        case EN_I2C_POLLACK:
            g_iI2CStatus = iicSt;
            break;

        case EN_I2C_RDDATA:
            if((g_iI2CDataCount--)==0)
            {
                g_ucI2CBuff[g_ucI2CPt++] = v_pIICReg->rIICDS;
            
                v_pIICReg->rIICSTAT = 0x90;             //Stop MasRx condition 
                v_pIICReg->rIICCON  = 0xe0;             //0xaf;                //Resumes IIC operation.	//hzh
                Delay(1);                       //Wait until stop condtion is in effect.
                                                //Too long time... 
                                                //The pending bit will not be set after issuing stop condition.
                break;    
            }      
            g_ucI2CBuff[g_ucI2CPt++] = v_pIICReg->rIICDS;
                        //The last data has to be read with no ack.
            if( (g_iI2CDataCount) == 0 )
                v_pIICReg->rIICCON = 0x60;//0x2f;                 //Resumes IIC operation with NOACK.  	//hzh
            else 
                v_pIICReg->rIICCON = 0xe0;//0xaf;                 //Resumes IIC operation with ACK	//hzh
            break;

        case EN_I2C_WRDATA:
            if( (g_iI2CDataCount--) == 0 )
            {
                v_pIICReg->rIICSTAT = 0xd0;                //stop MasTx condition 
                v_pIICReg->rIICCON  = 0xe0;//0xaf;                //resumes IIC operation.	//hzh
                Delay(1);                       //wait until stop condtion is in effect.
                       //The pending bit will not be set after issuing stop condition.
                break;    
            }
            v_pIICReg->rIICDS = g_ucI2CBuff[g_ucI2CPt++];        //_iicData[0] has dummy.
            for( i=0; i<10; i++ );                  //for setup time until rising edge of IICSCL
                v_pIICReg->rIICCON = 0xe0;          //0xaf;                     //resumes IIC operation.	//hzh
            break;

        case EN_I2C_SETRDADDR:
//            Uart_Printf("IicPoll() SETRADDR [S%d]",_iicDataCount);
            if( (g_iI2CDataCount--) == 0 )
            {
                break;                  //IIC operation is stopped because of IICCON[4]    
            }
            v_pIICReg->rIICDS = g_ucI2CBuff[g_ucI2CPt++];
            for( i=0; i<10; i++ );          //for setup time until rising edge of IICSCL
                v_pIICReg->rIICCON = 0xe0;  //0xaf;             //resumes IIC operation.	//hzh
            break;

        default:
            break;      
    }
}


//**************[ _Wr24C080 ]*****************************************
BOOL IIC_WriteByte(unsigned short uAddr, unsigned char ucData)
{

    g_dwI2CMode     = EN_I2C_WRDATA;
    g_ucI2CPt       = 0;
    g_ucI2CBuff[0]  = (unsigned char)uAddr;
    g_ucI2CBuff[1]  = ucData;
    g_iI2CDataCount = 2;
    
   
    
    v_pIICReg->rIICDS        = SLAVE_IIC_ADDR;            //0xa0
      //Master Tx mode, Start(Write), IIC-bus data output enable
      //Bus arbitration sucessful, Address as slave status flag Cleared,
      //Address zero status flag cleared, Last received bit is 0
    v_pIICReg->rIICSTAT      = 0xf0;      
      //Clearing the pending bit isn't needed because the pending bit has been cleared.
    while( g_iI2CDataCount != -1 )
       IIC_Poll();

    g_dwI2CMode = EN_I2C_POLLACK;

    while(1)
    {
        v_pIICReg->rIICDS     = SLAVE_IIC_ADDR;
        g_iI2CStatus = 0x100;             //To check if _iicStatus is changed 
        v_pIICReg->rIICSTAT   = 0xf0;              //Master Tx, Start, Output Enable, Sucessful, Cleared, Cleared, 0
        v_pIICReg->rIICCON    = 0xe0;//0xaf;              //Resumes IIC operation. //hzh
        while( g_iI2CStatus == 0x100 )  
            IIC_Poll();
              
        if( !(g_iI2CStatus & 0x1) )
            break;                      //When ACK is received
    }
    v_pIICReg->rIICSTAT = 0xd0;                    //Master Tx condition, Stop(Write), Output Enable
    v_pIICReg->rIICCON  = 0xe0;//0xaf;                    //Resumes IIC operation. 	//hzh
    Delay(1);                           //Wait until stop condtion is in effect.
      //Write is completed.
    return (TRUE);
}
        
//************************[ _Rd24C080 ]********************************
BOOL IIC_ReadByte(unsigned short uAddr, unsigned char* pucData )
{
    g_dwI2CMode     = EN_I2C_SETRDADDR;
    g_ucI2CPt       = 0;
    g_ucI2CBuff[0]  = (unsigned char)uAddr;
    g_iI2CDataCount = 1;

    v_pIICReg->rIICDS   = SLAVE_IIC_ADDR;
    v_pIICReg->rIICSTAT = 0xf0;                    //MasTx,Start  
      //Clearing the pending bit isn't needed because the pending bit has been cleared.
    while( g_iI2CDataCount != -1 )
        IIC_Poll();

    g_dwI2CMode     = EN_I2C_RDDATA;
    g_ucI2CPt       = 0;
    g_iI2CDataCount = 1;
    
    v_pIICReg->rIICDS   = SLAVE_IIC_ADDR;
    v_pIICReg->rIICSTAT = 0xb0;                    //Master Rx,Start
    v_pIICReg->rIICCON  = 0xe0;//0xaf;                    //Resumes IIC operation.	//hzh
    while( g_iI2CDataCount != -1 )
        IIC_Poll();

    *pucData = g_ucI2CBuff[1];
    return (TRUE);
}