?? project_0.plg
字號:
Current project is: 'project'
PSD Address Translation - Merge MCU Firmware with PSD
PSDsoft Express 8.30 Copyright (C) 1993-2004 STMicroelectronics, Inc. All Rights Reserved.
PROJECT : project DATE : 11/30/2004
DEVICE : uPSD3334D TIME : 16:49:31
>>
>> Address Translation complete.
>>
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'project'
Processing equations..............
Module parsing complete. Building logic network...
Creating Berkeley PLA file project.tt1...
Module 'project' processing complete.
Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'project'
Processing equations..............
Module parsing complete. Building logic network...
Creating Berkeley PLA file project.tt1...
Module 'project' processing complete.
Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds
BLIFOPT Open-ABEL Optimizer
U.C. Berkeley, SIS Ver. 1.0, modified by Data I/O Corp.
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Reading Open-ABEL (PLA) file project.tt1...
Performing 'bypin choose' optimization...
Shortening signal names...
Writing signal name cross reference file project.xrf...
Writing Open-ABEL (PLA) file project.tt2...
BLIFOPT complete - 0 errors, 0 warnings. Time: 1 seconds
DIOFFT Flip-Flop Transformation program
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Input file: project.tt2.
Output file: project.tt3.
DIOFFT complete. - Time 0 seconds
PSD Fitter - Logic Synthesis and Device Fitting
PSDsoft Express 8.30 Copyright (C) 1993-2004 STMicroelectronics, Inc. All Rights Reserved.
PROJECT : project DATE : 11/30/2004
DEVICE : uPSD3334D TIME : 16:52:55
FIT OPTION : Keep Current
DESCRIPTION: Example design for uPSD3334D to demonstrate the I2C bus slave
capabilities of the device.
Runs on DK3300-ELCD boards.
>> PSD Fitter complete - Successful Fitting
>> View fitter report for detail
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'project'
Processing equations..............
Module parsing complete. Building logic network...
Creating Berkeley PLA file project.tt1...
Module 'project' processing complete.
Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds
BLIFOPT Open-ABEL Optimizer
U.C. Berkeley, SIS Ver. 1.0, modified by Data I/O Corp.
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Reading Open-ABEL (PLA) file project.tt1...
Performing 'bypin choose' optimization...
Shortening signal names...
Writing signal name cross reference file project.xrf...
Writing Open-ABEL (PLA) file project.tt2...
BLIFOPT complete - 0 errors, 0 warnings. Time: 1 seconds
DIOFFT Flip-Flop Transformation program
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Input file: project.tt2.
Output file: project.tt3.
DIOFFT complete. - Time 0 seconds
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'project'
Processing equations..............
Module parsing complete. Building logic network...
Creating Berkeley PLA file project.tt1...
Module 'project' processing complete.
Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'project'
Processing equations..............
Module parsing complete. Building logic network...
Creating Berkeley PLA file project.tt1...
Module 'project' processing complete.
Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 2 seconds
BLIFOPT Open-ABEL Optimizer
U.C. Berkeley, SIS Ver. 1.0, modified by Data I/O Corp.
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Reading Open-ABEL (PLA) file project.tt1...
Performing 'bypin choose' optimization...
Shortening signal names...
Writing signal name cross reference file project.xrf...
Writing Open-ABEL (PLA) file project.tt2...
BLIFOPT complete - 0 errors, 0 warnings. Time: 1 seconds
DIOFFT Flip-Flop Transformation program
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Input file: project.tt2.
Output file: project.tt3.
DIOFFT complete. - Time 0 seconds
PSD Fitter - Logic Synthesis and Device Fitting
PSDsoft Express 8.30 Copyright (C) 1993-2004 STMicroelectronics, Inc. All Rights Reserved.
PROJECT : project DATE : 11/30/2004
DEVICE : uPSD3334D TIME : 16:54:16
FIT OPTION : Keep Current
DESCRIPTION: Example design for uPSD3334D to demonstrate the I2C bus slave
capabilities of the device.
Runs on DK3300-ELCD boards.
>> PSD Fitter complete - Successful Fitting
>> View fitter report for detail
Project 'project' is closed
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