?? twi.lst
字號:
A51 MACRO ASSEMBLER TWI 06/01/2004 16:22:44 PAGE 1
MACRO ASSEMBLER A51 V7.09
OBJECT MODULE PLACED IN twi.OBJ
ASSEMBLER INVOKED BY: C:\KEIL\C51\BIN\A51.EXE twi.a51 NOMOD51 SET(SMALL) DEBUG EP
LOC OBJ LINE SOURCE
1 ;$include (reg_c51.INC)
+1 2 +1 $save
+1 210 +1 $restore
211
212
0010 213 TWI_data DATA 10H;
0011 214 slave_adr DATA 11H;
0020 215 rw BIT 20H; /* 0=write, 1=read */
0021 216 b_TWI_busy BIT 21H;
217
0000 218 org 000h
0000 020100 219 ljmp begin
0043 220 org 43h
0043 020125 221 ljmp twi_it
222
223 ;/**
224 ; * FUNCTION_PURPOSE:this function setup TWI in master mode and sends data to slave.
225 ; * FUNCTION_INPUTS:void
226 ; * FUNCTION_OUTPUTS:void
227 ; */
0100 228 org 0100h
229
0100 230 begin:
231
0100 439340 232 ORL SSCON,#40h; /* enable TWI */
0103 D2AF 233 SETB EA; /* interrupt enable */
0105 43B102 234 ORL IEN1,#02h; /* enable TWI interrupt */
235
0108 C221 236 CLR b_TWI_busy
010A 237 loop:
238
010A 202116 239 JB b_TWI_busy,end_if
010D 8593E0 240 MOV ACC,SSCON
0110 20E410 241 JB ACC.4,end_if
242
0113 D221 243 SETB b_TWI_busy; /* flag busy =1 */
0115 751055 244 MOV TWI_data,#55h; /* data example to send */
0118 751101 245 MOV slave_adr,#01h; /* slave adresse example */
011B C220 246 CLR rw; /* 0=write */
011D 759500 247 MOV SSDAT,#00h; /* clear buffer before sending data */
0120 439320 248 ORL SSCON,#20h; /* TWI start sending */
249
0123 250 end_if:
251
252
0123 80E5 253 JMP loop
254
255 ;/**
256 ; * FUNCTION_PURPOSE:TWI interrupt, task witch process the different status of TWI
257 ; * FUNCTION_INPUTS:void
258 ; * FUNCTION_OUTPUTS:void
259 ; */
0125 260 twi_it:
0125 AF94 261 MOV R7,SSCS
262
263
264
0127 BF0004 265 CJNE R7,#00h,end_case_00
A51 MACRO ASSEMBLER TWI 06/01/2004 16:22:44 PAGE 2
266
012A C221 267 CLR b_TWI_busy; /* TWI is free */
012C 805D 268 JMP end_switch
012E 269 end_case_00:
270
271
012E BF0812 272 CJNE R7,#08h,end_case_08
273
0131 5393DF 274 ANL SSCON,#~20h; /* clear start condition */
275
0134 8511E0 276 MOV ACC,slave_adr
0137 23 277 RL A
0138 A220 278 MOV C,rw
013A 92E0 279 MOV ACC.0,C
013C F595 280 MOV SSDAT,A
281
013E 439304 282 ORL SSCON,#04h; /* set AA */
0141 8048 283 JMP end_switch
0143 284 end_case_08:
285
286
0143 BF1012 287 CJNE R7,#10h,end_case_10
288
0146 5393DF 289 ANL SSCON,#~20h; /* clear start condition */
290
0149 8511E0 291 MOV ACC,slave_adr
014C 23 292 RL A
014D A220 293 MOV C,rw
014F 92E0 294 MOV ACC.0,C
0151 F595 295 MOV SSDAT,A
296
0153 439304 297 ORL SSCON,#04h; /* set AA */
0156 8033 298 JMP end_switch
0158 299 end_case_10:
300
301
0158 BF1808 302 CJNE R7,#18h,end_case_18
015B 851095 303 MOV SSDAT,TWI_data; /* Transmit data byte, ACK bit received */
015E 439304 304 ORL SSCON,#04h; /* set AA */
0161 8028 305 JMP end_switch
0163 306 end_case_18:
307
0163 BF2007 308 CJNE R7,#20h,end_case_20
0166 439310 309 ORL SSCON,#10h; /* Transmit STOP */
0169 C221 310 CLR b_TWI_busy; /* TWI is free */
016B 801E 311 JMP end_switch
016D 312 end_case_20:
313
016D BF2807 314 CJNE R7,#28h,end_case_28
0170 439310 315 ORL SSCON,#10h; /* send STOP */
0173 C221 316 CLR b_TWI_busy; /* TWI is free */
0175 8014 317 JMP end_switch
0177 318 end_case_28:
319
0177 BF3007 320 CJNE R7,#30h,end_case_30
017A 439310 321 ORL SSCON,#10h; /* Transmit STOP */
017D C221 322 CLR b_TWI_busy; /* TWI is free */
017F 800A 323 JMP end_switch
0181 324 end_case_30:
325
0181 BF3807 326 CJNE R7,#38h,end_case_38
0184 439310 327 ORL SSCON,#10h; /* Transmit STOP */
0187 C221 328 CLR b_TWI_busy; /* TWI is free */
0189 8000 329 JMP end_switch
018B 330 end_case_38:
331
A51 MACRO ASSEMBLER TWI 06/01/2004 16:22:44 PAGE 3
018B 332 end_switch:
018B 5393F7 333 ANL SSCON,#~08; /* clear flag */
018E 32 334 RETI
335
336 end
A51 MACRO ASSEMBLER TWI 06/01/2004 16:22:44 PAGE 4
SYMBOL TABLE LISTING
------ ----- -------
N A M E T Y P E V A L U E ATTRIBUTES
AC . . . . . . . . B ADDR 00D0H.6 A
ACC. . . . . . . . D ADDR 00E0H A
AUXR . . . . . . . D ADDR 008EH A
AUXR1. . . . . . . D ADDR 00A2H A
B. . . . . . . . . D ADDR 00F0H A
BDRCON . . . . . . D ADDR 009BH A
BEGIN. . . . . . . C ADDR 0100H A
BRL. . . . . . . . D ADDR 009AH A
B_TWI_BUSY . . . . B ADDR 0024H.1 A
CCAP0H . . . . . . D ADDR 00FAH A
CCAP0L . . . . . . D ADDR 00EAH A
CCAP1H . . . . . . D ADDR 00FBH A
CCAP1L . . . . . . D ADDR 00EBH A
CCAP2H . . . . . . D ADDR 00FCH A
CCAP2L . . . . . . D ADDR 00ECH A
CCAP3H . . . . . . D ADDR 00FDH A
CCAP3L . . . . . . D ADDR 00EDH A
CCAP4H . . . . . . D ADDR 00FEH A
CCAP4L . . . . . . D ADDR 00EEH A
CCAPM0 . . . . . . D ADDR 00DAH A
CCAPM1 . . . . . . D ADDR 00DBH A
CCAPM2 . . . . . . D ADDR 00DCH A
CCAPM3 . . . . . . D ADDR 00DDH A
CCAPM4 . . . . . . D ADDR 00DEH A
CCF0 . . . . . . . B ADDR 00D8H.0 A
CCF1 . . . . . . . B ADDR 00D8H.1 A
CCF2 . . . . . . . B ADDR 00D8H.2 A
CCF3 . . . . . . . B ADDR 00D8H.3 A
CCF4 . . . . . . . B ADDR 00D8H.4 A
CCON . . . . . . . D ADDR 00D8H A
CF . . . . . . . . B ADDR 00D8H.7 A
CH . . . . . . . . D ADDR 00F9H A
CKCON0 . . . . . . D ADDR 008FH A
CKCON1 . . . . . . D ADDR 00AFH A
CKRL . . . . . . . D ADDR 0097H A
CKSEL. . . . . . . D ADDR 0085H A
CL . . . . . . . . D ADDR 00E9H A
CMOD . . . . . . . D ADDR 00D9H A
CP_RL2 . . . . . . B ADDR 00C8H.0 A
CR . . . . . . . . B ADDR 00D8H.6 A
CY . . . . . . . . B ADDR 00D0H.7 A
C_T2 . . . . . . . B ADDR 00C8H.1 A
DPH. . . . . . . . D ADDR 0083H A
DPL. . . . . . . . D ADDR 0082H A
EA . . . . . . . . B ADDR 00A8H.7 A
EC . . . . . . . . B ADDR 00A8H.6 A
EECON. . . . . . . D ADDR 00D2H A
END_CASE_00. . . . C ADDR 012EH A
END_CASE_08. . . . C ADDR 0143H A
END_CASE_10. . . . C ADDR 0158H A
END_CASE_18. . . . C ADDR 0163H A
END_CASE_20. . . . C ADDR 016DH A
END_CASE_28. . . . C ADDR 0177H A
END_CASE_30. . . . C ADDR 0181H A
END_CASE_38. . . . C ADDR 018BH A
END_IF . . . . . . C ADDR 0123H A
END_SWITCH . . . . C ADDR 018BH A
ES . . . . . . . . B ADDR 00A8H.4 A
ET0. . . . . . . . B ADDR 00A8H.1 A
ET1. . . . . . . . B ADDR 00A8H.3 A
A51 MACRO ASSEMBLER TWI 06/01/2004 16:22:44 PAGE 5
ET2. . . . . . . . B ADDR 00A8H.5 A
EX0. . . . . . . . B ADDR 00A8H.0 A
EX1. . . . . . . . B ADDR 00A8H.2 A
EXEN2. . . . . . . B ADDR 00C8H.3 A
EXF2 . . . . . . . B ADDR 00C8H.6 A
F0 . . . . . . . . B ADDR 00D0H.5 A
FCON . . . . . . . D ADDR 00D1H A
IE0. . . . . . . . B ADDR 0088H.1 A
IE1. . . . . . . . B ADDR 0088H.3 A
IEN0 . . . . . . . D ADDR 00A8H A
IEN1 . . . . . . . D ADDR 00B1H A
INT0 . . . . . . . B ADDR 00B0H.2 A
INT1 . . . . . . . B ADDR 00B0H.3 A
IPH0 . . . . . . . D ADDR 00B7H A
IPH1 . . . . . . . D ADDR 00B3H A
IPL0 . . . . . . . D ADDR 00B8H A
IPL1 . . . . . . . D ADDR 00B2H A
IT0. . . . . . . . B ADDR 0088H.0 A
IT1. . . . . . . . B ADDR 0088H.2 A
KBE. . . . . . . . D ADDR 009DH A
KBF. . . . . . . . D ADDR 009EH A
KBLS . . . . . . . D ADDR 009CH A
LOOP . . . . . . . C ADDR 010AH A
OSCCON . . . . . . D ADDR 0086H A
OV . . . . . . . . B ADDR 00D0H.2 A
P. . . . . . . . . B ADDR 00D0H.0 A
P0 . . . . . . . . D ADDR 0080H A
P1 . . . . . . . . D ADDR 0090H A
P2 . . . . . . . . D ADDR 00A0H A
P3 . . . . . . . . D ADDR 00B0H A
P4 . . . . . . . . D ADDR 00C0H A
P5 . . . . . . . . D ADDR 00E8H A
PCON . . . . . . . D ADDR 0087H A
PI2. . . . . . . . D ADDR 00F8H A
PI2_1. . . . . . . B ADDR 00F8H.1 A
PI2_O. . . . . . . B ADDR 00F8H.0 A
PPCL . . . . . . . B ADDR 00B8H.6 A
PSL. . . . . . . . B ADDR 00B8H.4 A
PSW. . . . . . . . D ADDR 00D0H A
PT0L . . . . . . . B ADDR 00B8H.1 A
PT1L . . . . . . . B ADDR 00B8H.3 A
PT2L . . . . . . . B ADDR 00B8H.5 A
PX0L . . . . . . . B ADDR 00B8H.0 A
PX1L . . . . . . . B ADDR 00B8H.2 A
RB8. . . . . . . . B ADDR 0098H.2 A
RCAP2H . . . . . . D ADDR 00CBH A
RCAP2L . . . . . . D ADDR 00CAH A
RCLK . . . . . . . B ADDR 00C8H.5 A
RD . . . . . . . . B ADDR 00B0H.7 A
REN. . . . . . . . B ADDR 0098H.4 A
RI . . . . . . . . B ADDR 0098H.0 A
RS0. . . . . . . . B ADDR 00D0H.3 A
RS1. . . . . . . . B ADDR 00D0H.4 A
RW . . . . . . . . B ADDR 0024H.0 A
RXD. . . . . . . . B ADDR 00B0H.0 A
SADDR. . . . . . . D ADDR 00A9H A
SADEN. . . . . . . D ADDR 00B9H A
SBUF . . . . . . . D ADDR 0099H A
SCON . . . . . . . D ADDR 0098H A
SLAVE_ADR. . . . . D ADDR 0011H A
SM0. . . . . . . . B ADDR 0098H.7 A
SM1. . . . . . . . B ADDR 0098H.6 A
SM2. . . . . . . . B ADDR 0098H.5 A
SP . . . . . . . . D ADDR 0081H A
SPCON. . . . . . . D ADDR 00C3H A
SPDAT. . . . . . . D ADDR 00C5H A
A51 MACRO ASSEMBLER TWI 06/01/2004 16:22:44 PAGE 6
SPSTA. . . . . . . D ADDR 00C4H A
SSADR. . . . . . . D ADDR 0096H A
SSCON. . . . . . . D ADDR 0093H A
SSCS . . . . . . . D ADDR 0094H A
SSDAT. . . . . . . D ADDR 0095H A
T0 . . . . . . . . B ADDR 00B0H.4 A
T1 . . . . . . . . B ADDR 00B0H.5 A
T2CON. . . . . . . D ADDR 00C8H A
T2MOD. . . . . . . D ADDR 00C9H A
TB8. . . . . . . . B ADDR 0098H.3 A
TCLK . . . . . . . B ADDR 00C8H.4 A
TCON . . . . . . . D ADDR 0088H A
TF0. . . . . . . . B ADDR 0088H.5 A
TF1. . . . . . . . B ADDR 0088H.7 A
TF2. . . . . . . . B ADDR 00C8H.7 A
TH0. . . . . . . . D ADDR 008CH A
TH1. . . . . . . . D ADDR 008DH A
TH2. . . . . . . . D ADDR 00CDH A
TI . . . . . . . . B ADDR 0098H.1 A
TL0. . . . . . . . D ADDR 008AH A
TL1. . . . . . . . D ADDR 008BH A
TL2. . . . . . . . D ADDR 00CCH A
TMOD . . . . . . . D ADDR 0089H A
TR0. . . . . . . . B ADDR 0088H.4 A
TR1. . . . . . . . B ADDR 0088H.6 A
TR2. . . . . . . . B ADDR 00C8H.2 A
TWI_DATA . . . . . D ADDR 0010H A
TWI_IT . . . . . . C ADDR 0125H A
TXD. . . . . . . . B ADDR 00B0H.1 A
WDTPRG . . . . . . D ADDR 00A7H A
WDTRST . . . . . . D ADDR 00A6H A
WR . . . . . . . . B ADDR 00B0H.6 A
REGISTER BANK(S) USED: 0
ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)
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