?? 2.4g+?
字號:
__start:
__text_start:
003F EFCF LDI R28,0xFF
0040 E0D2 LDI R29,2
0041 BFCD OUT 0x3D,R28
0042 BFDE OUT 0x3E,R29
0043 51C0 SUBI R28,0x10
0044 40D0 SBCI R29,0
0045 EA0A LDI R16,0xAA
0046 8308 STD Y+0,R16
0047 2400 CLR R0
0048 E4E9 LDI R30,0x49
0049 E0F1 LDI R31,1
004A E011 LDI R17,1
004B 35EE CPI R30,0x5E
004C 07F1 CPC R31,R17
004D F011 BEQ 0x0050
004E 9201 ST R0,Z+
004F CFFB RJMP 0x004B
0050 8300 STD Z+0,R16
0051 E3E4 LDI R30,0x34
0052 E0F0 LDI R31,0
0053 E0A0 LDI R26,0
0054 E0B1 LDI R27,1
0055 E010 LDI R17,0
0056 37ED CPI R30,0x7D
0057 07F1 CPC R31,R17
0058 F021 BEQ 0x005D
0059 95C8 LPM
005A 9631 ADIW R30,1
005B 920D ST R0,X+
005C CFF9 RJMP 0x0056
005D D001 RCALL _main
_exit:
005E CFFF RJMP _exit
_main:
Get_SO --> R20
005F 9721 SBIW R28,1
FILE: E:\項目\PS2無~1\progamme\acceptavrnrf24l01\acceptavrnrf24l01\main.c
(0001) //ICC-AVR application builder : 2006-02-12 14:00:00
(0002) // Target : ATmega48
(0003) // Crystal: 8.000Mhz
(0004) // Author: jackyan
(0005) // Oled Type : white
(0006) //#define fosc 8000000
(0007) //#define baud 9600
(0008) #include "iom48v.h"
(0009) #include "macros.h"
(0010) #include "defs.h"
(0011) /*-----------------------------------------------------------------------------
(0012) Global Defines
(0013) ------------------------------------------------------------------------------*/
(0014) unsigned char key_debug;
(0015) unsigned char Buffer[]={
(0016) 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
(0017) 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
(0018) 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
(0019) 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
(0020) };
(0021) #define TX_ADR_WIDTH 5 // 5 bytes TX(RX) address width
(0022) #define TX_PLOAD_WIDTH 20 // 16 bytes TX payload
(0023) unsigned char TX_ADDRESS[TX_ADR_WIDTH] = {0x34,0x43,0x10,0x10,0x01}; // Define a static TX address
(0024) void init_CPU (void);
(0025) void delayms(unsigned short dly);//當dly=1時，延時的時間是1ms 4MHz晶震
(0026) void INIT_io(void);
(0027) void RX_Mode(void);
(0028) void TX_Mode(void);
(0029) void delay(void);
(0030) unsigned char SPI_Write_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes);
(0031) unsigned char SPI_Read_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes);
(0032) unsigned char SPI_RW_Reg(unsigned char reg, unsigned char value);
(0033) unsigned char SPI_Read(unsigned char reg);
(0034) void clear_buf(unsigned char *ptr,unsigned char number);
(0035) unsigned char accept_flag=0;
(0036) unsigned char send_flag=0;
(0037) unsigned int accept_time=0;
(0038) void nrf24l01init(void);
(0039) //****************************************************************//
(0040) // SPI(nRF24L01) commands
(0041) #define READ_REG 0x00 // Define read command to register
(0042) #define WRITE_REG 0x20 // Define write command to register
(0043) #define RD_RX_PLOAD 0x61 // Define RX payload register address
(0044) #define WR_TX_PLOAD 0xA0 // Define TX payload register address
(0045) #define FLUSH_TX 0xE1 // Define flush TX register command
(0046) #define FLUSH_RX 0xE2 // Define flush RX register command
(0047) #define REUSE_TX_PL 0xE3 // Define reuse TX payload register command
(0048) //#define NOP 0xFF // Define No Operation, might be used to read status register
(0049) //***************************************************//
(0050) // SPI(nRF24L01) registers(addresses)
(0051) #define CONFIG 0x00 // 'Config' register address
(0052) #define EN_AA 0x01 // 'Enable Auto Acknowledgment' register address
(0053) #define EN_RXADDR 0x02 // 'Enabled RX addresses' register address
(0054) #define SETUP_AW 0x03 // 'Setup address width' register address
(0055) #define SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address
(0056) #define RF_CH 0x05 // 'RF channel' register address
(0057) #define RF_SETUP 0x06 // 'RF setup' register address
(0058) #define STATUS 0x07 // 'Status' register address
(0059) #define OBSERVE_TX 0x08 // 'Observe TX' register address
(0060) #define CD 0x09 // 'Carrier Detect' register address
(0061) #define RX_ADDR_P0 0x0A // 'RX address pipe0' register address
(0062) #define RX_ADDR_P1 0x0B // 'RX address pipe1' register address
(0063) #define RX_ADDR_P2 0x0C // 'RX address pipe2' register address
(0064) #define RX_ADDR_P3 0x0D // 'RX address pipe3' register address
(0065) #define RX_ADDR_P4 0x0E // 'RX address pipe4' register address
(0066) #define RX_ADDR_P5 0x0F // 'RX address pipe5' register address
(0067) #define TX_ADDR 0x10 // 'TX address' register address
(0068) #define RX_PW_P0 0x11 // 'RX payload width, pipe0' register address
(0069) #define RX_PW_P1 0x12 // 'RX payload width, pipe1' register address
(0070) #define RX_PW_P2 0x13 // 'RX payload width, pipe2' register address
(0071) #define RX_PW_P3 0x14 // 'RX payload width, pipe3' register address
(0072) #define RX_PW_P4 0x15 // 'RX payload width, pipe4' register address
(0073) #define RX_PW_P5 0x16 // 'RX payload width, pipe5' register address
(0074) #define FIFO_STATUS 0x17 // 'FIFO Status Register' register address
(0075) #define MAX_RT 0x10 // Max #of TX retrans interrupt
(0076) #define TX_DS 0x20 // TX data sent interrupt
(0077) #define RX_DR 0x40 // RX data received
(0078) //-----------------------------------------------------------------------------
(0079) //------------------------------------------------------
(0080) unsigned char t20ms;
(0081) #define BIT(x) (1 << (x))
(0082) #define SETBIT(x, y) (x |= y)
(0083) #define CLEARBIT(x, y) (x &= ~y)
(0084) #define CHECKBIT(x, y) (x & y)
(0085) #define BIT7 0x80
(0086) #define BIT6 0x40
(0087) #define BIT5 0x20
(0088) #define BIT4 0x10
(0089) #define BIT3 0x08
(0090) #define BIT2 0x04
(0091) #define BIT1 0x02
(0092) #define BIT0 0x01
(0093) #define nRF24L01_CSN BIT6
(0094) #define nRF24L01_SCK BIT7
(0095) #define nRF24L01_MOSI BIT0
(0096) #define nRF24L01_CE BIT5
(0097) #define nRF24L01_MISO BIT1
(0098) #define nRF24L01_IRQ BIT2
(0099) #define nRF24L01_CSNH SETBIT(PORTD, nRF24L01_CSN)
(0100) #define nRF24L01_CSNL CLEARBIT(PORTD, nRF24L01_CSN)
(0101)
(0102) #define nRF24L01_CSN_DIR SETBIT(DDRD, nRF24L01_CSN) //OUTPUT
(0103)
(0104) #define nRF24L01_SCKH SETBIT(PORTD,nRF24L01_SCK)
(0105) #define nRF24L01_SCKL CLEARBIT(PORTD,nRF24L01_SCK)
(0106) #define nRF24L01_SCK_DIR SETBIT(DDRD,nRF24L01_SCK) //OUTPUT
(0107)
(0108) #define nRF24L01_MOSIH SETBIT(PORTB,nRF24L01_MOSI)
(0109) #define nRF24L01_MOSIL CLEARBIT(PORTB,nRF24L01_MOSI)
(0110) #define nRF24L01_MOSI_DIR SETBIT(DDRB,nRF24L01_MOSI)
(0111)
(0112) #define nRF24L01_CEH SETBIT(PORTD,nRF24L01_CE) //OUTPUT
(0113) #define nRF24L01_CEL CLEARBIT(PORTD,nRF24L01_CE)
(0114) #define nRF24L01_CE_DIR SETBIT(DDRD,nRF24L01_CE)
(0115)
(0116) #define nRF24L01_IRQ_DIR CLEARBIT(DDRB,nRF24L01_IRQ) //INPUT
(0117)
(0118) #define nRF24L01_MISO_DIR CLEARBIT(DDRB,nRF24L01_MISO) //INPUT
(0119) #define key1 BIT5
(0120) #define key2 BIT6
(0121) #define key3 BIT7
(0122) #define key4 BIT0
(0123) #define key5 BIT1
(0124) #define key6 BIT2
(0125) #define bit20ms BIT0
(0126) unsigned char flag;
(0127) unsigned char key1_pulse;
(0128) unsigned char key2_pulse;
(0129) unsigned char key3_pulse;
(0130) unsigned char key4_pulse;
(0131) unsigned char key5_pulse;
(0132) unsigned char key6_pulse;
(0133) unsigned char key1_flag;
(0134) unsigned char key2_flag;
(0135) unsigned char key3_flag;
(0136) unsigned char key4_flag;
(0137) unsigned char key5_flag;
(0138) unsigned char key6_flag;
(0139) unsigned char send_flag;
(0140) unsigned char key1_time;
(0141) unsigned char key2_time;
(0142) unsigned char key3_time;
(0143) unsigned char key4_time;
(0144) unsigned char key5_time;
(0145) unsigned char key6_time;
(0146)
(0147) //-----------------------------------------------------------------------------
(0148) void main(void)
(0149) {
(0150) unsigned char Get_SO=0;
0060 2744 CLR R20
(0151) CLI(); /* global interrupt disable */
0061 94F8 BCLR 7
(0152) init_CPU ();
0062 D067 RCALL _init_CPU
(0153) delayms(100); //延時10ms*10=100ms
0063 E604 LDI R16,0x64
0064 E010 LDI R17,0
0065 D08C RCALL _delayms
(0154) delayms(100); //延時10ms*10=100ms
0066 E604 LDI R16,0x64
0067 E010 LDI R17,0
0068 D089 RCALL _delayms
(0155) RX_Mode();
0069 D100 RCALL _RX_Mode
(0156) send_flag=0;
006A 2422 CLR R2
006B 92200146 STS send_flag,R2
006D C052 RJMP 0x00C0
(0157) while(1)
(0158) {
(0159) // if(!(PINB& 0x01))
(0160) WDR();
006E 95A8 WDR
(0161) if(!(PINB& nRF24L01_IRQ))
006F 991A SBIC 0x03,2
0070 C022 RJMP 0x0093
(0162) {//nRF24L01 接收數據
(0163) key_debug=SPI_Read(STATUS); // read register STATUS's value
0071 E007 LDI R16,7
0072 D0B7 RCALL _SPI_Read
0073 9300015D STS key_debug,R16
(0164) if(key_debug&RX_DR) // if renRF24L01_CEive data ready (RX_DR) interrupt
0075 FF06 SBRS R16,6
0076 C006 RJMP 0x007D
(0165) SPI_Read_Buf(RD_RX_PLOAD,Buffer,TX_PLOAD_WIDTH);// read renRF24L01_CEive payload from RX_FIFO buffer
0077 E184 LDI R24,0x14
0078 8388 STD Y+0,R24
0079 E020 LDI R18,0
007A E031 LDI R19,1
007B E601 LDI R16,0x61
007C D0BB RCALL _SPI_Read_Buf
(0166) if(key_debug&MAX_RT) SPI_RW_Reg(FLUSH_TX,0);
007D 9020015D LDS R2,key_debug
007F FE24 SBRS R2,4
0080 C003 RJMP 0x0084
0081 2722 CLR R18
0082 EE01 LDI R16,0xE1
0083 D097 RCALL _SPI_RW_Reg
(0167) SPI_RW_Reg(WRITE_REG+STATUS,0xff);// clear RX_DR or TX_DS or MAX_RT interrupt flag
0084 EF2F LDI R18,0xFF
0085 E207 LDI R16,0x27
0086 D094 RCALL _SPI_RW_Reg
(0168) RX_Mode();
0087 D0E2 RCALL _RX_Mode
(0169) if((Buffer[0]==80)&&(Buffer[1]==02))//data accept
0088 91800100 LDS R24,Buffer
008A 3580 CPI R24,0x50
008B F439 BNE 0x0093
008C 91800101 LDS R24,Buffer+1
008E 3082 CPI R24,2
008F F419 BNE 0x0093
(0170) {
(0171) accept_flag=1;
0090 E081 LDI R24,1
0091 93800145 STS accept_flag,R24
(0172) // PORTB = 0x80;
(0173) // delayms(5000); //延時10ms*10=100ms
(0174) // PORTB = 0x00;
(0175) }
(0176) }
(0177) if(send_flag==1)
0093 91800146 LDS R24,send_flag
0095 3081 CPI R24,1
0096 F4D1 BNE 0x00B1
(0178) {
(0179) accept_time++;
0097 91800147 LDS R24,accept_time
0099 91900148 LDS R25,accept_time+1
009B 9601 ADIW R24,1
009C 93900148 STS accept_time+1,R25
009E 93800147 STS accept_time,R24
(0180) // PORTB = 0x00;
(0181) if(accept_time>1000)
00A0 EE88 LDI R24,0xE8
00A1 E093 LDI R25,3
00A2 90200147 LDS R2,accept_time
00A4 90300148 LDS R3,accept_time+1
00A6 1582 CP R24,R2
00A7 0593 CPC R25,R3
00A8 F440 BCC 0x00B1
(0182) {
(0183) send_flag=0;
00A9 2422 CLR R2
00AA 92200146 STS send_flag,R2
(0184) accept_time=0;
00AC 2433 CLR R3
00AD 92300148 STS accept_time+1,R3
00AF 92200147 STS accept_time,R2
(0185) }
(0186) }
(0187) if(accept_flag==1)
00B1 91800145 LDS R24,accept_flag
00B3 3081 CPI R24,1
00B4 F459 BNE 0x00C0
(0188) {
(0189) accept_flag=0;
00B5 2422 CLR R2
00B6 92200145 STS accept_flag,R2
(0190) PORTB = 0x80;
00B8 E880 LDI R24,0x80
00B9 B985 OUT 0x05,R24
(0191) delayms(1000); //延時10ms*10=100ms
00BA EE08 LDI R16,0xE8
00BB E013 LDI R17,3
00BC D035 RCALL _delayms
(0192) PORTB = 0x00;
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