?? 2.4g+?
字號:
; RX Mode, set RX address, writes RX payload width,
; select RF channel, datarate & LNA HCURR.
; After init, CE is toggled high, which means that
; this device is now ready to receive a datapacket. */
; /**************************************************/
; void RX_Mode(void)
; {
.dbline 393
; nRF24L01_CEL;
cbi 0xb,5
.dbline 394
; delay();
rcall _delay
.dbline 395
; SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // Use the same address on the RX device as the TX device
ldi R24,5
std y+0,R24
ldi R18,<_TX_ADDRESS
ldi R19,>_TX_ADDRESS
ldi R16,42
rcall _SPI_Write_Buf
.dbline 397
;
; SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // Enable Auto.Ack:Pipe0
ldi R18,1
ldi R16,33
rcall _SPI_RW_Reg
.dbline 398
; SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0
ldi R18,1
ldi R16,34
rcall _SPI_RW_Reg
.dbline 399
; SPI_RW_Reg(WRITE_REG + RF_CH, 40); // Select RF channel 40
ldi R18,40
ldi R16,37
rcall _SPI_RW_Reg
.dbline 400
; SPI_RW_Reg(WRITE_REG + RX_PW_P0, TX_PLOAD_WIDTH); // Select same RX payload width as TX Payload width
ldi R18,20
ldi R16,49
rcall _SPI_RW_Reg
.dbline 401
; SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07); // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
ldi R18,7
ldi R16,38
rcall _SPI_RW_Reg
.dbline 402
; SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:RX. RX_DR enabled..
ldi R18,15
ldi R16,32
rcall _SPI_RW_Reg
.dbline 403
; nRF24L01_CEH;
sbi 0xb,5
.dbline 404
; delay();
rcall _delay
.dbline -2
L62:
adiw R28,1
.dbline 0 ; func end
ret
.dbend
.dbfunc e TX_Mode _TX_Mode fV
.even
_TX_Mode::
sbiw R28,1
.dbline -1
.dbline 424
; // This device is now ready to receive one packet of 16 bytes payload from a TX device sending to address
; // '3443101001', with auto acknowledgment, retransmit count of 10, RF channel 40 and datarate = 2Mbps.
;
; }
; /**************************************************/
;
; /**************************************************
; Function: TX_Mode();
;
; Description:
; This function initializes one nRF24L01 device to
; TX mode, set TX address, set RX address for auto.ack,
; fill TX payload, select RF channel, datarate & TX pwr.
; PWR_UP is set, CRC(2 bytes) is enabled, & PRIM:TX.
;
; ToDo: One high pulse(>10us) on CE will now send this
; packet and expext an acknowledgment from the RX device. */
; /**************************************************/
; void TX_Mode(void)
; {
.dbline 425
; nRF24L01_CEL;
cbi 0xb,5
.dbline 426
; delay();
rcall _delay
.dbline 427
; SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); // Writes TX_Address to nRF24L01
ldi R24,5
std y+0,R24
ldi R18,<_TX_ADDRESS
ldi R19,>_TX_ADDRESS
ldi R16,48
rcall _SPI_Write_Buf
.dbline 428
; SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // RX_Addr0 same as TX_Adr for Auto.Ack
ldi R24,5
std y+0,R24
ldi R18,<_TX_ADDRESS
ldi R19,>_TX_ADDRESS
ldi R16,42
rcall _SPI_Write_Buf
.dbline 429
; SPI_Write_Buf(WR_TX_PLOAD, Buffer, TX_PLOAD_WIDTH); // Writes data to TX payload
ldi R24,20
std y+0,R24
ldi R18,<_Buffer
ldi R19,>_Buffer
ldi R16,160
rcall _SPI_Write_Buf
.dbline 431
;
; SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // Enable Auto.Ack:Pipe0
ldi R18,1
ldi R16,33
rcall _SPI_RW_Reg
.dbline 432
; SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0
ldi R18,1
ldi R16,34
rcall _SPI_RW_Reg
.dbline 433
; SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0x1a); // 500us + 86us, 10 retrans...
ldi R18,26
ldi R16,36
rcall _SPI_RW_Reg
.dbline 434
; SPI_RW_Reg(WRITE_REG + RF_CH, 40); // Select RF channel 40
ldi R18,40
ldi R16,37
rcall _SPI_RW_Reg
.dbline 435
; SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07); // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
ldi R18,7
ldi R16,38
rcall _SPI_RW_Reg
.dbline 436
; SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:TX. MAX_RT & TX_DS enabled..
ldi R18,14
ldi R16,32
rcall _SPI_RW_Reg
.dbline 437
; nRF24L01_CEH;
sbi 0xb,5
.dbline 438
; delay();
rcall _delay
.dbline -2
L63:
adiw R28,1
.dbline 0 ; func end
ret
.dbend
.dbfunc e timer0_init _timer0_init fV
.even
_timer0_init::
.dbline -1
.dbline 443
;
; }
; //------------------------------------------------------
; void timer0_init(void)
; {
.dbline 444
; TCCR0B = 0x00; //stop
clr R2
out 0x25,R2
.dbline 445
; TCNT0 = 0x06; //set count
ldi R24,6
out 0x26,R24
.dbline 446
; TCCR0A = 0x00;
out 0x24,R2
.dbline 447
; TCCR0B = 0x02; //start timer
ldi R24,2
out 0x25,R24
.dbline -2
L64:
.dbline 0 ; func end
ret
.dbend
.area vector(rom, abs)
.org 32
rjmp _timer0_ovf_isr
.area text(rom, con, rel)
.dbfile E:\項(xiàng)目\PS2無~1\progamme\sendavrnrf24l01\sendavrnrf24l01\main.c
.dbfunc e timer0_ovf_isr _timer0_ovf_isr fV
.even
_timer0_ovf_isr::
st -y,R2
st -y,R3
st -y,R24
st -y,R25
in R2,0x3f
st -y,R2
.dbline -1
.dbline 451
; }
; #pragma interrupt_handler timer0_ovf_isr:17
; void timer0_ovf_isr(void) // 5ms
; {
.dbline 453
;
; TCNT0 = 0x06; //reload counter value
ldi R24,6
out 0x26,R24
.dbline 455
;
; if((--t20ms)==0)
lds R24,_t20ms
subi R24,1
mov R2,R24
sts _t20ms,R2
tst R24
breq X2
rjmp L66
X2:
.dbline 456
; {
.dbline 457
; set(flag,bit20ms);
.dbline 457
lds R24,_flag
ori R24,1
sts _flag,R24
.dbline 457
.dbline 457
.dbline 458
; t20ms=t20msC;
ldi R24,20
sts _t20ms,R24
.dbline 459
; if(PIND& key1)
sbis 0x9,4
rjmp L68
.dbline 460
; {
.dbline 461
; key1_pulse<<=1;
lds R2,_key1_pulse
lsl R2
sts _key1_pulse,R2
.dbline 462
; key1_pulse&=0xfe;
mov R24,R2
andi R24,254
sts _key1_pulse,R24
.dbline 463
; }
L68:
.dbline 464
; if(!(PIND& key1))
sbic 0x9,4
rjmp L70
.dbline 465
; {
.dbline 466
; key1_pulse<<=1;
lds R2,_key1_pulse
lsl R2
sts _key1_pulse,R2
.dbline 467
; key1_pulse|=0x01;
mov R24,R2
ori R24,1
sts _key1_pulse,R24
.dbline 468
; }
L70:
.dbline 469
; if(key1_pulse==0x0f)
lds R24,_key1_pulse
cpi R24,15
brne L72
.dbline 470
; {
.dbline 471
; key1_flag=1;
ldi R24,1
sts _key1_flag,R24
.dbline 472
; send_flag=1;
sts _send_flag,R24
.dbline 473
; accept_time=0;
clr R2
clr R3
sts _accept_time+1,R3
sts _accept_time,R2
.dbline 474
; }
L72:
.dbline 475
; if(key1_pulse==0xff)
lds R24,_key1_pulse
cpi R24,255
brne L74
.dbline 476
; {
.dbline 477
; key1_time++;
lds R24,_key1_time
subi R24,255 ; addi 1
sts _key1_time,R24
.dbline 478
; if(key1_time>10)
ldi R24,10
lds R2,_key1_time
cp R24,R2
brsh L76
.dbline 479
; {
.dbline 480
; key1_time=0;
clr R2
sts _key1_time,R2
.dbline 481
; key1_flag=1;
ldi R24,1
sts _key1_flag,R24
.dbline 482
; send_flag=1;
sts _send_flag,R24
.dbline 483
; accept_time=0;
clr R3
sts _accept_time+1,R3
sts _accept_time,R2
.dbline 484
; }
L76:
.dbline 485
; }
L74:
.dbline 486
; if(PIND& key2)
sbis 0x9,3
rjmp L78
.dbline 487
; {
.dbline 488
; key2_pulse<<=1;
lds R2,_key2_pulse
lsl R2
sts _key2_pulse,R2
.dbline 489
; key2_pulse&=0xfe;
mov R24,R2
andi R24,254
sts _key2_pulse,R24
.dbline 490
; }
L78:
.dbline 491
; if(!(PIND& key2))
sbic 0x9,3
rjmp L80
.dbline 492
; {
.dbline 493
; key2_pulse<<=1;
lds R2,_key2_pulse
lsl R2
sts _key2_pulse,R2
.dbline 494
; key2_pulse|=0x01;
mov R24,R2
ori R24,1
sts _key2_pulse,R24
.dbline 495
; }
L80:
.dbline 496
; if(key2_pulse==0x0f)
lds R24,_key2_pulse
cpi R24,15
brne L82
.dbline 497
; {
.dbline 498
; key2_flag=1;
ldi R24,1
sts _key2_flag,R24
.dbline 499
; send_flag=1;
sts _send_flag,R24
.dbline 500
; accept_time=0;
clr R2
clr R3
sts _accept_time+1,R3
sts _accept_time,R2
.dbline 501
; }
L82:
.dbline 502
; if(key2_pulse==0xff)
lds R24,_key2_pulse
cpi R24,255
brne L84
.dbline 503
; {
.dbline 504
; key2_time++;
lds R24,_key2_time
subi R24,255 ; addi 1
sts _key2_time,R24
.dbline 505
; if(key2_time>10)
ldi R24,10
lds R2,_key2_time
cp R24,R2
brsh L86
.dbline 506
; {
.dbline 507
; key2_time=0;
clr R2
sts _key2_time,R2
.dbline 508
; key2_flag=1;
ldi R24,1
sts _key2_flag,R24
.dbline 509
; send_flag=1;
sts _send_flag,R24
.dbline 510
; accept_time=0;
clr R3
sts _accept_time+1,R3
sts _accept_time,R2
.dbline 511
; }
L86:
.dbline 512
; }
L84:
.dbline 513
; if(PIND& key3)
sbis 0x9,2
rjmp L88
.dbline 514
; {
.dbline 515
; key3_pulse<<=1;
lds R2,_key3_pulse
lsl R2
sts _key3_pulse,R2
.dbline 516
; key3_pulse&=0xfe;
mov R24,R2
andi R24,254
sts _key3_pulse,R24
.dbline 517
; }
L88:
.dbline 518
; if(!(PIND& key3))
sbic 0x9,2
rjmp L90
.dbline 519
; {
.dbline 520
; key3_pulse<<=1;
lds R2,_key3_pulse
lsl R2
sts _key3_pulse,R2
.dbline 521
; key3_pulse|=0x01;
mov R24,R2
ori R24,1
sts _key3_pulse,R24
.dbline 522
; }
L90:
.dbline 523
; if(key3_pulse==0x0f)
lds R24,_key3_pulse
cpi R24,15
brne L92
.dbline 524
; {
.dbline 525
; key3_flag=1;
ldi R24,1
sts _key3_flag,R24
.dbline 526
; send_flag=1;
sts _send_flag,R24
.dbline 527
; accept_time=0;
clr R2
clr R3
sts _accept_time+1,R3
sts _accept_time,R2
.dbline 528
; }
L92:
.dbline 529
; if(key3_pulse==0xff)
lds R24,_key3_pulse
cpi R24,255
brne L94
.dbline 530
; {
.dbline 531
; key3_time++;
lds R24,_key3_time
subi R24,255 ; addi 1
sts _key3_time,R24
.dbline 532
; if(key3_time>10)
ldi R24,10
lds R2,_key3_time
cp R24,R2
brsh L96
.dbline 533
; {
.dbline 534
; key3_time=0;
clr R2
sts _key3_time,R2
.dbline 535
; key3_flag=1;
ldi R24,1
sts _key3_flag,R24
.dbline 536
; send_flag=1;
sts _send_flag,R24
.dbline 537
; accept_time=0;
clr R3
sts _accept_time+1,R3
sts _accept_time,R2
.dbline 538
; }
L96:
.dbline 539
; }
L94:
.dbline 540
; if(PINC& key4)
sbis 0x6,5
rjmp L98
.dbline 541
; {
.dbline 542
; key4_pulse<<=1;
lds R2,_key4_pulse
lsl R2
sts _key4_pulse,R2
.dbline 543
; key4_pulse&=0xfe;
mov R24,R2
andi R24,254
sts _key4_pulse,R24
.dbline 544
; }
L98:
.dbline 545
; if(!(PINC& key4))
sbic 0x6,5
rjmp L100
.dbline 546
; {
.dbline 547
; key4_pulse<<=1;
lds R2,_key4_pulse
lsl R2
sts _key4_pulse,R2
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