?? tonecfg_c.c
字號(hào):
/* Do *not* directly modify this file. It was *//* generated by the Configuration Tool; any *//* changes risk being overwritten. *//* INPUT tone.cdb *//* Include Header File */#include "tonecfg.h"extern Uint16 dst, dst;extern Uint16 src;/* Config Structures */DMA_Config dmaCfg0 = { 0x0001, /* Channel Priority (0x0000 or 0x0001) */ 0x0001, /* Global Reload Register Usage in Autoinit Mode (AUTOIX : 0x0000 or 0x0001) */ 0x504d, /* Transfer Mode Control Register (DMMCR) */ 0x3800, /* Sync Event and Frame Count Register (DMSFC) */ (DMA_AdrPtr)0x0030, /* Source Address Register (DMSRC) - Numeric */ (DMA_AdrPtr)&dst, /* Destination Address Register (DMDST) - Symbolic */ 0x0140, /* Element Count Register (DMCTR) */ (DMA_AdrPtr)0x0030, /* Global Source Address Reload Register (DMGSA) - Numeric */ (DMA_AdrPtr)&dst, /* Global Destination Address Reload Register (DMGDA) - Symbolic */ 0x004f, /* Global Element Count Reload Register (DMGCR) */ 0x0000 /* Global Frame Count Reload Register (DMGFR) */};DMA_Config dmaCfg1 = { 0x0000, /* Channel Priority (0x0000 or 0x0001) */ 0x0000, /* Global Reload Register Usage in Autoinit Mode (AUTOIX : 0x0000 or 0x0001) */ 0x5341, /* Transfer Mode Control Register (DMMCR) */ 0x4800, /* Sync Event and Frame Count Register (DMSFC) */ (DMA_AdrPtr)&src, /* Source Address Register (DMSRC) - Symbolic */ (DMA_AdrPtr)0x0032, /* Destination Address Register (DMDST) - Numeric */ 0x0140, /* Element Count Register (DMCTR) */ NULL, /* Global Source Address Reload Register (DMGSA) - Symbolic */ NULL, /* Global Destination Address Reload Register (DMGDA) - Symbolic */ 0x0000, /* Global Element Count Reload Register (DMGCR) */ 0x0000 /* Global Frame Count Reload Register (DMGFR) */};DMA_GblConfig gDMAConfig0 = { 0x0, /* Breakpoint Emulation Behavior (FREE) */ 0x0001, /* Global Reload Register Usage in Autoinit Mode (AUTOIX : 0x0000 or 0x0001) */ 0x00, /* Source Program Page Address Register (DMSRCP) - Numeric */ NULL, /* Destination Program Page Address Register (DMDSTP) - Symbolic */ 0x0001, /* Element Address Index Register 0 (DMIDX0) */ 0x0000, /* Frame Address Index Register 0 (DMFRI0) */ 0x0000, /* Element Address Index Register 1 (DMIDX1) */ 0x0000, /* Frame Address Index Register 1 (DMFRI1) */ 0x00, /* Extended Source Data Page Register (DMSRCDP) - Numeric */ (Uint16)&dst /* Extended Destination Data Page Register (DMDSTDP) - Symbolic */};DMA_GblConfig gDMAConfig1 = { 0x0, /* Breakpoint Emulation Behavior (FREE) */ 0x0000, /* Global Reload Register Usage in Autoinit Mode (AUTOIX : 0x0000 or 0x0001) */ NULL, /* Source Program Page Address Register (DMSRCP) - Symbolic */ 0x00, /* Destination Program Page Address Register (DMDSTP) - Numeric */ 0x0001, /* Element Address Index Register 0 (DMIDX0) */ 0x0000, /* Frame Address Index Register 0 (DMFRI0) */ 0x0001, /* Element Address Index Register 1 (DMIDX1) */ 0x0000, /* Frame Address Index Register 1 (DMFRI1) */ (Uint16)&src, /* Extended Source Data Page Register (DMSRCDP) - Symbolic */ 0x00 /* Extended Destination Data Page Register (DMDSTDP) - Numeric */};MCBSP_Config mcbspCfg0 = { 0x2000, /* Serial Port Control Register 1 */ 0x0000, /* Serial Port Control Register 2 */ 0x01a0, /* Receive Control Register 1 */ 0x0000, /* Receive Control Register 2 */ 0x01a0, /* Transmit Control Register 1 */ 0x0000, /* Transmit Control Register 2 */ 0x1f00, /* Sample Rate Generator Register 1 */ 0x003f, /* Sample Rate Generator Register 2 */ 0x0000, /* Multichannel Control Register 1 */ 0x0000, /* Multichannel Control Register 2 */ 0x0083, /* Pin Control Register */ 0x0000, /* Receive Channel Enable Register Partition A */ 0x0000, /* Receive Channel Enable Register Partition B */ 0x0000, /* Receive Channel Enable Register Partition C */ 0x0000, /* Receive Channel Enable Register Partition D */ 0x0000, /* Receive Channel Enable Register Partition E */ 0x0000, /* Receive Channel Enable Register Partition F */ 0x0000, /* Receive Channel Enable Register Partition G */ 0x0000, /* Receive Channel Enable Register Partition H */ 0x0000, /* Transmit Channel Enable Register Partition A */ 0x0000, /* Transmit Channel Enable Register Partition B */ 0x0000, /* Transmit Channel Enable Register Partition C */ 0x0000, /* Transmit Channel Enable Register Partition D */ 0x0000, /* Transmit Channel Enable Register Partition E */ 0x0000, /* Transmit Channel Enable Register Partition F */ 0x0000, /* Transmit Channel Enable Register Partition G */ 0x0000 /* Transmit Channel Enable Register Partition H */};/* Handles */DMA_Handle hDma2;DMA_Handle hDma3;MCBSP_Handle C54XX_DMA_MCBSP_hMcbsp;/* * ======== CSL_cfgInit() ======== */void CSL_cfgInit(){ dmaCfg0.dmdst = (DMA_AdrPtr)((Uint32)(&dst) & 0xFFFF); gDMAConfig0.gbldmdstdp = (Uint16)((Uint32)(&dst) >> 16); dmaCfg1.dmsrc = (DMA_AdrPtr)((Uint32)(&src) & 0xFFFF); gDMAConfig1.gbldmsrcdp = (Uint16)((Uint32)(&src) >> 16); hDma2 = DMA_open(DMA_CHA2, DMA_OPEN_RESET); hDma3 = DMA_open(DMA_CHA3, DMA_OPEN_RESET); C54XX_DMA_MCBSP_hMcbsp = MCBSP_open(MCBSP_PORT2, MCBSP_OPEN_RESET); DMA_config(hDma2, &dmaCfg1); DMA_globalConfig(0x0FFFF, &gDMAConfig1); DMA_config(hDma3, &dmaCfg0); DMA_globalConfig(0x0FFFF, &gDMAConfig0); MCBSP_config(C54XX_DMA_MCBSP_hMcbsp, &mcbspCfg0);}
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