#ifndef __INTEL82527_CAN_H__
#define __INTEL82527_CAN_H__

#include "linux/types.h"

/* The following statements will be for the can bus and intel 82527 */
typedef struct canmessage{
  uint8_t	msgCtrl0Reg;	
	uint8_t	msgCtrl1Reg;
  uint8_t	idReg[4];
	uint8_t	messageConfigReg;
	uint8_t	dataReg[8];         /* data bytes   */
} canmessageobj_t __attribute__ ((packed));

typedef struct {
  uint32_t id;
  int type;                   /* standard or extended frame */
  int rtr;                    /* remote transmission        */
  int len;                    /* data length 0..8           */
  unsigned char d[8];         /* data bytes                 */
  struct timeval timestamp;   /* timestamp                  */
} canmsg;

#define STANDARD 0
#define EXTENDED 1

#define DATAFRAME 0
#define REMOTEFRAME 1

#define ACTIVE	0
#define PASSIVE	1
#define BUSOFF 2

#define BUFFER_SIZE 150
#define MSG_LENGTH  sizeof(canmsg)

typedef struct CAN_Dev {
  int baud_rate;		     	/* baud rate of the bus            */
  int frame_mode;		     	/* normal (0) or extended (1) mode */
  int active_passive_status;   	/* current state of the controller */
  int isopen;                   	/* user application counter        */
  
  int rb_full_counter;         	/* read_buffer full counter (protection against too many interrupts FIXME wtf? */
  
  canmsg read_buf[BUFFER_SIZE];
  int nm_rb;			/* number of messages in the read buffer */
  int rp_rb;			/* read position of the read buffer	 */	
  int wp_rb;			/* write position of the read buffer	 */
  
  canmsg write_buf[BUFFER_SIZE];
  int nm_wb;                     	/* number of messages in the write buffer */
  int wp_wb;                     	/* write position of the write buffer	  */
  int rp_wb;                     	/* read position of the write buffer	  */

  unsigned char *reg_base;
}CAN_Dev;

#define CAN_TIM0_10K		  49
#define CAN_TIM1_10K		0x1c
#define CAN_TIM0_20K		  24	
#define CAN_TIM1_20K		0x1c
#define CAN_TIM0_40K		0x89	/* Old Bit Timing Standard of port */
#define CAN_TIM1_40K		0xEB	/* Old Bit Timing Standard of port */
#define CAN_TIM0_50K		   9
#define CAN_TIM1_50K		0x1c
#define CAN_TIM0_100K      4    /* sp 87%, 16 abtastungen, sjw 1 */
#define CAN_TIM1_100K   0x1c
#define CAN_TIM0_125K		   3
#define CAN_TIM1_125K		0x1c
#define CAN_TIM0_250K		   1
#define CAN_TIM1_250K		0x1c
#define CAN_TIM0_500K		   0
#define CAN_TIM1_500K		0x1c
#define CAN_TIM0_800K		   0
#define CAN_TIM1_800K		0x16
#define CAN_TIM0_1000K		 0
#define CAN_TIM1_1000K	0x14

uint8_t iCanTiming[10][2]={
	{CAN_TIM0_10K,  CAN_TIM1_10K},
	{CAN_TIM0_20K,  CAN_TIM1_20K},
	{CAN_TIM0_40K,  CAN_TIM1_40K},
	{CAN_TIM0_50K,  CAN_TIM1_50K},
	{CAN_TIM0_100K, CAN_TIM1_100K},
	{CAN_TIM0_125K, CAN_TIM1_125K},
	{CAN_TIM0_250K, CAN_TIM1_250K},
	{CAN_TIM0_500K, CAN_TIM1_500K},
	{CAN_TIM0_800K, CAN_TIM1_800K},
	{CAN_TIM0_1000K,CAN_TIM1_1000K}};

#define B1000	0  /* 1 MBit/s   */
#define B500	1  /* 500 Kbit/s */
#define B250	2  /* 250 Kbit/s */
#define B125	3  /* 125 Kbit/s */
#define B20	  4  /* 20 Kbit/s  */

#define iCTL 0x00		// Control Register
#define iSTAT 0x01		// Status Register
#define iCPU 0x02		// CPU Interface Register
#define iHSR 0x04		// High Speed Read
#define iSGM0 0x06		// Standard Global Mask byte 0
#define iSGM1 0x07
#define iEGM0 0x08		// Extended Global Mask byte 0
#define iEGM1 0x09
#define iEGM2 0x0a
#define iEGM3 0x0b
#define i15M0 0x0c		// Message 15 Mask byte 0
#define i15M1 0x0d
#define i15M2 0x0e
#define i15M3 0x0f
#define iMSGOBJ1 0x10
#define iCLK 0x1f	// Clock Out Register
#define iMSGOBJ2 0x20
#define iBUS 0x2f		// Bus Configuration Register
#define iMSGOBJ3 0x30
#define iBT0 0x3f		// Bit Timing Register byte 0
#define iMSGOBJ4 0x40
#define iBT1 0x4f
#define iMSGOBJ5 0x50
#define iIRQ 0x5f		// Interrupt Register
#define iMSGOBJ6 0x60
#define iMSGOBJ7 0x70
#define iMSGOBJ8 0x80
#define iMSGOBJ9 0x90
#define iP1C 0x9f		// Port 1 Register
#define iMSGOBJ10 0xA0
#define iP2C 0xaf		// Port 2 Register
#define iMSGOBJ11 0xB0
#define iP1I 0xbf		// Port 1 Data In Register
#define iMSGOBJ12 0xC0
#define iP2I 0xcf		// Port 2 Data In Register
#define iMSGOBJ13 0xD0
#define iP1O 0xdf		// Port 1 Data Out Register
#define iMSGOBJ14 0xE0
#define iP2O 0xef		// Port 2 Data Out Register
#define iMSGOBJ15 0xF0
#define iSRA 0xff		// Serial Reset Address

#define iMSGCTL0	0x00	/* First Control register */
#define iMSGCTL1	0x01	/* Second Control register */
#define iMSGID0		0x02	/* First Byte of Message ID */
#define iMSGID1		0x03
#define iMSGID2		0x04
#define iMSGID3		0x05
#define iMSGCFG		0x06	/* Message Configuration */
#define iMSGDAT0	0x07	/* First Data Byte */
#define iMSGDAT1	0x08
#define iMSGDAT2	0x09
#define iMSGDAT3	0x0a
#define iMSGDAT4	0x0b
#define iMSGDAT5	0x0c
#define iMSGDAT6	0x0d
#define iMSGDAT7	0x0e

/* Control Register (0x00) */
enum i82527_iCTL {
	iCTL_INI = 1,		// Initialization
	iCTL_IE  = 1<<1,	// Interrupt Enable
	iCTL_SIE = 1<<2,	// Status Interrupt Enable
	iCTL_EIE = 1<<3,	// Error Interrupt Enable
	iCTL_CCE = 1<<6		// Change Configuration Enable
};

/* Status Register (0x01) */
enum i82527_iSTAT {
	iSTAT_TXOK = 1<<3,	// Transmit Message Successfully
	iSTAT_RXOK = 1<<4,	// Receive Message Successfully
	iSTAT_WAKE = 1<<5,	// Wake Up Status
	iSTAT_WARN = 1<<6,	// Warning Status
	iSTAT_BOFF = 1<<7	// Bus Off Status
};

#define No_Error 0
#define Stuff_Error 1
#define Form_Error 2
#define Ack_Error 3
#define Bit1_Error 4
#define Bit0_Error 5
#define CRC_Error 6
#define Unused 7

/* CPU Interface Register (0x02) */
enum i82527_iCPU {
	iCPU_CEN = 1,		// Clock Out Enable
	iCPU_MUX = 1<<2,	// Multiplex
	iCPU_SLP = 1<<3,	// Sleep
	iCPU_PWD = 1<<4,	// Power Down Mode
	iCPU_DMC = 1<<5,	// Divide Memory Clock
	iCPU_DSC = 1<<6,	// Divide System Clock
	iCPU_RST = 1<<7		// Hardware Reset Status
};

/* Clock Out Register (0x1f) */
enum i82527_iCLK {
	iCLK_CD0 = 1,		// Clock Divider bit 0
	iCLK_CD1 = 1<<1,
	iCLK_CD2 = 1<<2,
	iCLK_CD3 = 1<<3,
	iCLK_SL0 = 1<<4,	// Slew Rate bit 0
	iCLK_SL1 = 1<<5
};

/* Bus Configuration Register (0x2f) */
enum i82527_iBUS {
	iBUS_DR0 = 1,		// Disconnect RX0 Input
	iBUS_DR1 = 1<<1,	// Disconnect RX1 Input
	iBUS_DT1 = 1<<3,	// Disconnect TX1 Output
	iBUS_POL = 1<<5,	// Polarity
	iBUS_CBY = 1<<6		// Comparator Bypass
};

#define RESET 1			// Bit Pair Reset Status
#define SET 2			// Bit Pair Set Status
#define UNCHANGED 3		// Bit Pair Unchanged

/* Message Control Register 0 (Base Address + 0x0) */
enum i82527_iMSGCTL0 {
	INTPD_SET = SET,		// Interrupt pending
	INTPD_RES = RESET,		// No Interrupt pending
	INTPD_UNC = UNCHANGED,
	RXIE_SET  = SET<<2,		// Receive Interrupt Enable
	RXIE_RES  = RESET<<2,		// Receive Interrupt Disable
	RXIE_UNC  = UNCHANGED<<2,
	TXIE_SET  = SET<<4,		// Transmit Interrupt Enable
	TXIE_RES  = RESET<<4,		// Transmit Interrupt Disable
	TXIE_UNC  = UNCHANGED<<4,
	MVAL_SET  = SET<<6,		// Message Valid
	MVAL_RES  = RESET<<6,		// Message Invalid
	MVAL_UNC  = UNCHANGED<<6
};

/* Message Control Register 1 (Base Address + 0x01) */
enum i82527_iMSGCTL1 {
	NEWD_SET = SET,			// New Data
	NEWD_RES = RESET,		// No New Data
	NEWD_UNC = UNCHANGED,
	MLST_SET = SET<<2,		// Message Lost
	MLST_RES = RESET<<2,		// No Message Lost
	MLST_UNC = UNCHANGED<<2,
	CPUU_SET = SET<<2,		// CPU Updating
	CPUU_RES = RESET<<2,		// No CPU Updating
	CPUU_UNC = UNCHANGED<<2,
	TXRQ_SET = SET<<4,		// Transmission Request
	TXRQ_RES = RESET<<4,		// No Transmission Request
	TXRQ_UNC = UNCHANGED<<4,
	RMPD_SET = SET<<6,		// Remote Request Pending
	RMPD_RES = RESET<<6,		// No Remote Request Pending
	RMPD_UNC = UNCHANGED<<6
};

/* Message Configuration Register (Base Address + 0x06) */
enum i82527_iMSGCFG {
	MCFG_XTD = 1<<2,		// Extended Identifier
	MCFG_DIR = 1<<3			// Direction is Transmit
};

/** The following statements will be for the main file **/
static int ican_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg);
static unsigned int ican_poll(struct file *filp, poll_table *wait);
static int ican_open(struct inode *inode, struct file *filp);
static int ican_release(struct inode *inode, struct file *filp);
static ssize_t ican_read(struct file *filp, char *buf, size_t count, loff_t *f_pos);
static ssize_t ican_write(struct file *filp, const char *buf, size_t count, loff_t *f_pos);


#define CAN_MAJOR	     91
#define REGBASE1  0x78200000  /* address for first intel82527 */
#define REGBASE2  0x78400000  /* address for second intel82527 */
#define IO_RANGE  0xFF

#define INT_REG 0x78600001
#define IRQ_NUM   0x13

unsigned char* int_reg;
struct timeval transmit_timestamp;

#define	CAN_NUMBER	2
CAN_Dev canDev[CAN_NUMBER];
int RxErr[CAN_NUMBER];
int TxErr[CAN_NUMBER];

/** These are for ioctl function **/
#define ICAN_IOC_BASE 'g'
#define ICAN_IOC_SBAUD					_IOW(ICAN_IOC_BASE,  1, 8)
#define ICAN_IOC_MASK					  _IOW(ICAN_IOC_BASE,  2, 8)
#define ICAN_IOC_CRBUF					_IOW(ICAN_IOC_BASE,  3, 8)
#define ICAN_IOC_CWBUF					_IOW(ICAN_IOC_BASE,  4, 8)#define ICAN_IOC_RREG						_IOR(ICAN_IOC_BASE,  5, 8)
#define ICAN_IOC_RTTS						_IOR(ICAN_IOC_BASE,  6, 8)
#define ICAN_IOC_RAPS						_IOR(ICAN_IOC_BASE,  7, 8)
#define ICAN_IOC_SBTR						_IOW(ICAN_IOC_BASE,  8, 8)
#define ICAN_IOC_START					_IOW(ICAN_IOC_BASE,  9, 8)
#define	ICAN_IOC_STOP						_IOW(ICAN_IOC_BASE,  10, 8)
#define ICAN_IOC_RESET					_IOW(ICAN_IOC_BASE,  11, 8)
#define ICAN_IOC_CONF_FILTER		_IOW(ICAN_IOC_BASE,  12, 8)
#define ICAN_IOC_SEND						_IOW(ICAN_IOC_BASE,  13, 8)
#define ICAN_IOC_RECEIVE				_IOW(ICAN_IOC_BASE,  14, 8)

#define CAN_IOC_MAXNR 14

#endif