?? video_test.c
字號:
#include "davincievm_i2c.h"
#include "davincievm.h"
#define TVP5150_I2C_ADDR_L 0x5D
#define TVP5150_I2C_ADDR_H 0x5C
Uint16 temp;
Uint32 temp1,temp2[5];
Uint16 tmp;
/* ------------------------------------------------------------------------ *
* *
* tvp5146_rset *
* *
* Set codec register regnum to value regval *
* *
* ------------------------------------------------------------------------ */
void tvp5150_rset( Uint8 regnum, Uint8 regval,Uint8 channel )
{
Uint8 cmd[2];
cmd[0] = regnum; // 8-bit Register Address
cmd[1] = regval; // 8-bit Register Data
switch (channel)
{
case 1:
temp=DAVINCIEVM_I2C_write( TVP5150_I2C_ADDR_L, cmd, 2);
break;
case 2:
temp=DAVINCIEVM_I2C_write( TVP5150_I2C_ADDR_H, cmd, 2);
break;
case 3:
{
temp=DAVINCIEVM_I2C_write( TVP5150_I2C_ADDR_L, cmd, 2);
temp=DAVINCIEVM_I2C_write( TVP5150_I2C_ADDR_H, cmd, 2);
break;
}
default:
break;
}
}
/* ------------------------------------------------------------------------ *
* *
* tvp5146_rget *
* *
* Return value of codec register regnum *
* *
* ------------------------------------------------------------------------ */
Uint8 tvp5150_rget( Uint8 regnum, Uint8 channel )
{
Uint8 cmd[2];
cmd[0] = regnum; // 8-bit Register Address
cmd[1] = 0; // 8-bit Register Data
switch (channel)
{
case 1:
{
DAVINCIEVM_I2C_write ( TVP5150_I2C_ADDR_L, cmd, 1 );
DAVINCIEVM_I2C_read ( TVP5150_I2C_ADDR_L, cmd, 1 );
break;
}
case 2:
DAVINCIEVM_I2C_write ( TVP5150_I2C_ADDR_H, cmd, 1 );
DAVINCIEVM_I2C_read ( TVP5150_I2C_ADDR_H, cmd, 1 );
break;
case 3:
DAVINCIEVM_I2C_write ( TVP5150_I2C_ADDR_L, cmd, 1 );
DAVINCIEVM_I2C_read ( TVP5150_I2C_ADDR_L, cmd, 1 );
DAVINCIEVM_I2C_write ( TVP5150_I2C_ADDR_H, cmd, 1 );
DAVINCIEVM_I2C_read ( TVP5150_I2C_ADDR_H, cmd, 1 );
break;
default:
break;
}
return cmd[0];
}
/* ------------------------------------------------------------------------ *
* *
* tvp5146_init( ) *
* *
* Initialize the TVP5146 *
* *
* ------------------------------------------------------------------------ */
void tvp5150_init(Uint8 channel,Uint8 mode)
{
DAVINCIEVM_GPIO_setDirection(39,0);
DAVINCIEVM_GPIO_setDirection(41,0);
switch (channel)
{
case 1:
{
DAVINCIEVM_GPIO_setOutput(39,0);
DAVINCIEVM_GPIO_setOutput(41,1);
break;
}
case 2:
{
DAVINCIEVM_GPIO_setOutput(39,1);
DAVINCIEVM_GPIO_setOutput(41,0);
break;
}
case 3:
{
DAVINCIEVM_GPIO_setOutput(39,1);
DAVINCIEVM_GPIO_setOutput(41,1);
break;
}
}
DAVINCIEVM_waitusec( 1000 );
switch(mode)
{
case 1:
{
tvp5150_rset( 0x00, 0x00, channel ); // Input Video: CVBS : VI_2_B
tvp5150_rset( 0x03, 0x6d, channel );
tvp5150_rset( 0x09, 0x8B, channel );
tvp5150_rset( 0x0a, 0x80, channel );
tvp5150_rset( 0x0b, 0x00, channel );
tvp5150_rset( 0x0D, 0x07, channel ); // Enabling clock & Y/CB/CR input format
tvp5150_rset( 0x0F, 0x02, channel );
tvp5150_rset( 0x15, 0x04, channel );
tvp5150_rset( 0x19, 0x01, channel ); //linger raw
tvp5150_rset( 0x1B, 0x14, channel );
break;
}
default:
{
tvp5150_rset( 0x00, 0x00, channel ); // Input Video: CVBS : VI_2_B
tvp5150_rset( 0x03, 0x6d, channel );
tvp5150_rset( 0x09, 0x8B, channel );
tvp5150_rset( 0x0a, 0x80, channel );
tvp5150_rset( 0x0b, 0x00, channel );
tvp5150_rset( 0x0D, 0x07, channel ); // Enabling clock & Y/CB/CR input format
tvp5150_rset( 0x0F, 0x02, channel );
tvp5150_rset( 0x15, 0x05, channel );
tvp5150_rset( 0x1B, 0x14, channel );
break;
}
}
DAVINCIEVM_waitusec( 1000 ); // wait 1 msec
}
#define NTSC 1
#if NTSC
#define BASEP_X 0x7A // 122
#define BASEP_Y 0x12 // 18
#elif PAL
#define BASEP_X 0x84 // 132
#define BASEP_Y 0x16 // 22
#endif
/* ------------------------------------------------------------------------ *
* *
* vpfe_init( ) *
* *
* NTSC: *
* Width: 720 *
* Height: 480 *
* *
* *
* ------------------------------------------------------------------------ */
void vpfe_init( Uint32 buffer, Uint32 width, Uint32 height,Uint8 channel )
{
switch (channel)
{
case 1:
{
VPFE_SYN_MODE = 0x00032F87; // interlaced, with VD pority as negative
VPFE_HD_VD_WID = 0;
VPFE_PIX_LINES = 0; //linger 720x624
/*
* sph = 1, nph = 1440, according to page 32-33 of the CCDC spec
* for BT.656 mode, this setting captures only the 720x480 of the
* active NTSV video window
*/
VPFE_HORZ_INFO = width << 1; // Horizontal lines
VPFE_HSIZE_OFF = width << 1; // Horizontal line offset
VPFE_VERT_START = 0; // Vertical start line
VPFE_VERT_LINES = height >> 1; // Vertical lines
VPFE_CULLING = 0xFFFF00FF; // Disable cullng
/*
* Interleave the two fields
*/
VPFE_SDOFST = 0x00000249;
VPFE_SDR_ADDR = buffer;
VPFE_CLAMP = 0;
VPFE_DCSUB = 0;
VPFE_COLPTN = 0xEE44EE44;
VPFE_BLKCMP = 0;
VPFE_FPC_ADDR = 0x86800000;
VPFE_FPC = 0;
VPFE_VDINT = 0;
VPFE_ALAW = 0;
VPFE_REC656IF = 0x00000003;
/*
* Input format is Cb:Y:Cr:Y, w/ Y in odd-pixel position
*/
VPFE_CCDCFG = 0x00008800;
VPFE_FMTCFG = 0x00008000; //linger
VPFE_FMT_HORZ = 0x000002D0;
VPFE_FMT_VERT = 0x00000240;//0x00000272;
VPFE_FMT_ADDR0 = 0;
VPFE_FMT_ADDR1 = 0;
VPFE_FMT_ADDR2 = 0;
VPFE_FMT_ADDR3 = 0;
VPFE_FMT_ADDR4 = 0;
VPFE_FMT_ADDR5 = 0;
VPFE_FMT_ADDR6 = 0;
VPFE_FMT_ADDR7 = 0;
VPFE_PRGEVEN_0 = 0;
VPFE_PRGEVEN_1 = 0;
VPFE_PRGODD_0 = 0;
VPFE_PRGODD_1 = 0;
VPFE_VP_OUT = 0x04E22D00;
VPFE_PCR = 0x00000001; // Enable CCDC
break;
}
case 2:
{
VPFE_SYN_MODE = 0x00030084; //linger interlaced, with VD pority as negative
VPFE_HD_VD_WID = 0;
VPFE_PIX_LINES = 0; //linger 720x625
/*
* sph = 1, nph = 1440, according to page 32-33 of the CCDC spec
* for BT.656 mode, this setting captures only the 720x480 of the
* active NTSV video window
*/
VPFE_HORZ_INFO = width << 1; // Horizontal lines
VPFE_HSIZE_OFF = width << 1; // Horizontal line offset
VPFE_VERT_START = 0; // Vertical start line
VPFE_VERT_LINES = height >> 1; // Vertical lines
VPFE_CULLING = 0xFFFF00FF; // Disable cullng
/*
* Interleave the two fields
*/
VPFE_SDOFST = 0x00000249;
VPFE_SDR_ADDR = buffer;
VPFE_CLAMP = 0;
VPFE_DCSUB = 0;
VPFE_COLPTN = 0xEE44EE44;
VPFE_BLKCMP = 0;
VPFE_FPC_ADDR = 0x86800000;
VPFE_FPC = 0;
VPFE_VDINT = 0;
VPFE_ALAW = 0;
VPFE_REC656IF = 0x00000002; //linger
/*
* Input format is Cb:Y:Cr:Y, w/ Y in odd-pixel position
*/
VPFE_CCDCFG = 0x00000800;
VPFE_FMTCFG = 0x00008000; //linger
VPFE_FMT_HORZ = 0x000002D0;
VPFE_FMT_VERT = 0x00000272;
VPFE_FMT_ADDR0 = 0;
VPFE_FMT_ADDR1 = 0;
VPFE_FMT_ADDR2 = 0;
VPFE_FMT_ADDR3 = 0;
VPFE_FMT_ADDR4 = 0;
VPFE_FMT_ADDR5 = 0;
VPFE_FMT_ADDR6 = 0;
VPFE_FMT_ADDR7 = 0;
VPFE_PRGEVEN_0 = 0;
VPFE_PRGEVEN_1 = 0;
VPFE_PRGODD_0 = 0;
VPFE_PRGODD_1 = 0;
VPFE_VP_OUT = 0x04e22D00;
VPFE_PCR = 0x00000001; // Enable CCDC
break;
}
case 3:
{
VPFE_SYN_MODE = 0x00030F84; //linger interlaced, with VD pority as negative
VPFE_HD_VD_WID = 0;
VPFE_PIX_LINES = 0; //linger 720x625
/*
* sph = 1, nph = 1440, according to page 32-33 of the CCDC spec
* for BT.656 mode, this setting captures only the 720x480 of the
* active NTSV video window
*/
VPFE_HORZ_INFO = 0x6C0;
VPFE_HSIZE_OFF = 0x6C0;
VPFE_VERT_START = 0; // Vertical start line
VPFE_VERT_LINES = 0x271>>1; // Vertical lines
VPFE_CULLING = 0xFFFF00FF; // Disable cullng
/*
* Interleave the two fields
*/
VPFE_SDOFST = 0x00000249;
VPFE_SDR_ADDR = buffer;
VPFE_CLAMP = 0;
VPFE_DCSUB = 0;
VPFE_COLPTN = 0xEE44EE44;
VPFE_BLKCMP = 0;
VPFE_FPC_ADDR = 0x86800000;
VPFE_FPC = 0;
VPFE_VDINT = 0;
VPFE_ALAW = 0;
VPFE_REC656IF = 0x00000002; //linger
/*
* Input format is Cb:Y:Cr:Y, w/ Y in odd-pixel position
*/
VPFE_CCDCFG = 0x00000800;
VPFE_FMTCFG = 0x00008000; //linger
VPFE_FMT_HORZ = 0x000002D0;
VPFE_FMT_VERT = 0x00000272;
VPFE_FMT_ADDR0 = 0;
VPFE_FMT_ADDR1 = 0;
VPFE_FMT_ADDR2 = 0;
VPFE_FMT_ADDR3 = 0;
VPFE_FMT_ADDR4 = 0;
VPFE_FMT_ADDR5 = 0;
VPFE_FMT_ADDR6 = 0;
VPFE_FMT_ADDR7 = 0;
VPFE_PRGEVEN_0 = 0;
VPFE_PRGEVEN_1 = 0;
VPFE_PRGODD_0 = 0;
VPFE_PRGODD_1 = 0;
VPFE_VP_OUT = 0x04e22D00;
VPFE_PCR = 0x00000001; // Enable CCDC
break;
}
default:
break;
}
}
/* ------------------------------------------------------------------------ *
* *
* vpbe_init( ) *
* *
* NTSC: *
* Width: 720 *
* Height: 480 *
* *
* *
* ------------------------------------------------------------------------ */
void vpbe_init( Uint32 buffer, Uint32 width, Uint32 height, Uint32 cb_enable,Uint8 mode )
{
/*
* Setup VPBE
*/
switch(mode)
{
case 1:
{
VPSS_CLK_CTRL = 0x00000018; // Enable DAC and VENC clock, both at 27 MHz
VPBE_PCR = 0; // No clock div, clock enable
/*
* Setup OSD
*/
OSD_MODE = 0x0000007f; // Blackground color blue using clut in ROM0
OSD_OSDWIN0MD = 0; // Disable both osd windows and cursor window
OSD_OSDWIN1MD = 0;
OSD_RECTCUR = 0;
OSD_VIDWIN0OFST = width >> 4;
OSD_VIDWIN0ADR = buffer;
OSD_BASEPX = BASEP_X;
OSD_BASEPY = BASEP_Y;
OSD_VIDWIN0XP = 0;
OSD_VIDWIN0YP = 0;
OSD_VIDWIN0XL = width;
OSD_VIDWIN0YL = height; //linger:full height
OSD_MISCCTL = 0;
OSD_VIDWINMD = 0x00000007; // linger width X2
// Frame mode with no up-scaling
/*
* Setup VENC
*/
VENC_VMOD = 0x00002103; //linger 60HZ 854x525
VENC_VIOCTL = 0x00002000;
VENC_VDPRO = 0x00000870|(cb_enable << 8);
VENC_DACTST = 0x00000000;
VENC_CMPNT = 0x00008000;
VENC_DACSEL = 0x00000435;
VENC_SYNCCTL = 0x00000003;
VENC_HSTART = 0x0;
VENC_HVALID = 0x0;
VENC_VSTART = 0x0;
VENC_VVALID = 0x0;
VENC_OSDCLK0 = 0x0;
VENC_OSDCLK1 = 0x1;
VENC_ARGBX0 = 1024;
VENC_ARGBX1 = 1404;
VENC_ARGBX2 = 345;
VENC_ARGBX3 = 715;
VENC_ARGBX4 = 1774;
VENC_RGBCTL = 0x00000000;
break;
}
default:
{
VPSS_CLK_CTRL = 0x00000018; // Enable DAC and VENC clock, both at 27 MHz
VPBE_PCR = 0; // No clock div, clock enable
/*
* Setup OSD
*/
OSD_MODE = 0x0000007f; // Blackground color blue using clut in ROM0
OSD_OSDWIN0MD = 0; // Disable both osd windows and cursor window
OSD_OSDWIN1MD = 0;
OSD_RECTCUR = 0;
OSD_VIDWIN0OFST = width >> 4;
OSD_VIDWIN0ADR = buffer;
OSD_BASEPX = BASEP_X;
OSD_BASEPY = BASEP_Y;
OSD_VIDWIN0XP = 0;
OSD_VIDWIN0YP = 0;
OSD_VIDWIN0XL = width;
OSD_VIDWIN0YL = height >> 1;
OSD_MISCCTL = 0;
OSD_VIDWINMD = 0x00000003; // Disable vwindow 1 and enable vwindow 0
// Frame mode with no up-scaling
/*
* Setup VENC
*/
VENC_VMOD = 0x00000043; // Standard NTSC interlaced output
VENC_VDPRO = cb_enable << 8;
VENC_DACTST = 0;
VENC_DACSEL = 0x000213;
break;
}
}
}
/* ------------------------------------------------------------------------ *
* *
* video_loopback_test( ) *
* *
* *
* *
* ------------------------------------------------------------------------ */
Int16 video_loopback_test( )
{
tvp5150_init(1,0);
vpfe_init( 0x81000000, 720, 480, 1); // Setup Front-End
vpbe_init( 0x81000000, 720, 480, 0, 1); // Setup Back-End
return 0;
}
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