?? dsp2833x_swprioritizedisrlevels.h
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// TI File $Revision: /main/2 $
// Checkin $Date: April 4, 2007 14:25:21 $
//###########################################################################
//
// FILE: DSP2833x_SWPrioritizedIsrLevels.h
//
// TITLE: DSP28 Devices Software Prioritized Interrupt Service Routine
// Level definitions.
//
//###########################################################################
// $TI Release: DSP2833x Header Files V1.01 $
// $Release Date: September 26, 2007 $
//###########################################################################
#ifndef DSP2833x_SW_PRIORITZIED_ISR_H
#define DSP2833x_SW_PRIORITZIED_ISR_H
#ifdef __cplusplus
extern "C" {
#endif
//-------------------------------------------------------------------------------
// Interrupt Enable Register Allocation For 2833x Devices:
//-------------------------------------------------------------------------------
// Interrupts can be enabled/disabled using the CPU interrupt enable register
// (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12).
//-------------------------------------------------------------------------------
//-------------------------------------------------------------------------------
// Set "Global" Interrupt Priority Level (IER register):
//-------------------------------------------------------------------------------
// The user must set the appropriate priority level for each of the CPU
// interrupts. This is termed as the "global" priority. The priority level
// must be a number between 1 (highest) to 16 (lowest). A value of 0 must
// be entered for reserved interrupts or interrupts that are not used. This
// will also reduce code size by not including ISR's that are not used.
//
// Note: The priority levels below are used to calculate the IER register
// interrupt masks MINT1 to MINT16.
//
//
// Note: The priority levels shown here may not make sense in a
// real application. This is for demonstration purposes only!!!
//
// The user should change these to values that make sense for
// their application.
//
// 0 = not used
// 1 = highest priority
// ...
// 16 = lowest priority
#define INT1PL 2 // Group1 Interrupts (PIEIER1)
#define INT2PL 1 // Group2 Interrupts (PIEIER2)
#define INT3PL 4 // Group3 Interrupts (PIEIER3)
#define INT4PL 2 // Group4 Interrupts (PIEIER4)
#define INT5PL 2 // Group5 Interrupts (PIEIER5)
#define INT6PL 3 // Group6 Interrupts (PIEIER6)
#define INT7PL 0 // reserved
#define INT8PL 0 // reserved
#define INT9PL 3 // Group9 Interrupts (PIEIER9)
#define INT10PL 0 // reserved
#define INT11PL 0 // reserved
#define INT12PL 0 // reserved
#define INT13PL 4 // XINT13
#define INT14PL 4 // INT14 (TINT2)
#define INT15PL 4 // DATALOG
#define INT16PL 4 // RTOSINT
//-------------------------------------------------------------------------------
// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers):
//-------------------------------------------------------------------------------
// The user must set the appropriate priority level for each of the PIE
// interrupts. This is termed as the "group" priority. The priority level
// must be a number between 1 (highest) to 8 (lowest). A value of 0 must
// be entered for reserved interrupts or interrupts that are not used. This
// will also reduce code size by not including ISR's that are not used:
//
// Note: The priority levels below are used to calculate the following
// PIEIER register interrupt masks:
// MG11 to MG18
// MG21 to MG28
// MG31 to MG38
// MG41 to MG48
// MG51 to MG58
// MG61 to MG68
// MG71 to MG78
// MG81 to MG88
// MG91 to MG98
// MG101 to MG108
// MG111 to MG118
// MG121 to MG128
//
// Note: The priority levels shown here may not make sense in a
// real application. This is for demonstration purposes only!!!
//
// The user should change these to values that make sense for
// their application.
//
// 0 = not used
// 1 = highest priority
// ...
// 8 = lowest priority
//
#define G11PL 7 // SEQ1INT (ADC)
#define G12PL 6 // SEQ2INT (ADC)
#define G13PL 0 // reserved
#define G14PL 1 // XINT1 (External)
#define G15PL 3 // XINT2 (External)
#define G16PL 2 // ADCINT (ADC)
#define G17PL 1 // TINT0 (CPU Timer 0)
#define G18PL 5 // WAKEINT (WD/LPM)
#define G21PL 4 // EPWM1_TZINT (ePWM1 Trip)
#define G22PL 3 // EPWM2_TZINT (ePWM2 Trip)
#define G23PL 2 // EPWM3_TZINT (ePWM3 Trip)
#define G24PL 1 // EPWM4_TZINT (ePWM4 Trip)
#define G25PL 5 // EPWM5_TZINT (ePWM5 Trip)
#define G26PL 6 // EPWM6_TZINT (ePWM6 Trip)
#define G27PL 0 // reserved
#define G28PL 0 // reserved
#define G31PL 4 // EPWM1_INT (ePWM1 Int)
#define G32PL 1 // EPWM2_INT (ePWM2 Int)
#define G33PL 1 // EPWM3_INT (ePWM3 Int)
#define G34PL 2 // EPWM4_INT (ePWM4 Int)
#define G35PL 2 // EPWM5_INT (ePWM5 Int)
#define G36PL 1 // EPWM6_INT (ePWM6 Int)
#define G37PL 0 // reserved
#define G38PL 0 // reserved
#define G41PL 2 // ECAP1_INT (eCAP1 Int)
#define G42PL 1 // ECAP2_INT (eCAP2 Int)
#define G43PL 3 // ECAP3_INT (eCAP3 Int)
#define G44PL 3 // ECAP4_INT (eCAP4 Int)
#define G45PL 5 // ECAP5_INT (eCAP5 Int)
#define G46PL 5 // ECAP6_INT (eCAP6 Int)
#define G47PL 0 // reserved
#define G48PL 0 // reserved
#define G51PL 2 // EQEP1_INT (eQEP1 Int)
#define G52PL 1 // EQEP2_INT (eQEP2 Int)
#define G53PL 0 // reserved
#define G54PL 0 // reserved
#define G55PL 0 // reserved
#define G56PL 0 // reserved
#define G57PL 0 // reserved
#define G58PL 0 // reserved
#define G61PL 3 // SPIRXINTA (SPI-A)
#define G62PL 1 // SPITXINTA (SPI-A)
#define G63PL 4 // MRINTB (McBSP-B)
#define G64PL 6 // MXINTB (McBSP-B)
#define G65PL 2 // MRINTA (McBSP-A)
#define G66PL 1 // MXINTA (McBSP-A)
#define G67PL 0 // reserved
#define G68PL 0 // reserved
#define G71PL 5 // DINTCH1 (DMA)
#define G72PL 4 // DINTCH2 (DMA)
#define G73PL 4 // DINTCH3 (DMA)
#define G74PL 2 // DINTCH4 (DMA)
#define G75PL 3 // DINTCH5 (DMA)
#define G76PL 1 // DINTCH6 (DMA)
#define G77PL 0 // reserved
#define G78PL 0 // reserved
#define G81PL 1 // I2CINT1A (I2C-A)
#define G82PL 2 // I2CINT2A (I2C-A)
#define G83PL 0 // reserved
#define G84PL 0 // reserved
#define G85PL 4 // SCIRXINTC (SCI-C)
#define G86PL 3 // SCITXINTC (SCI-C)
#define G87PL 0 // reserved
#define G88PL 0 // reserved
#define G91PL 1 // SCIRXINTA (SCI-A)
#define G92PL 5 // SCITXINTA (SCI-A)
#define G93PL 3 // SCIRXINTB (SCI-B)
#define G94PL 4 // SCITXINTB (SCI-B)
#define G95PL 1 // ECAN0INTA (ECAN-A)
#define G96PL 1 // ECAN1INTA (ECAN-A)
#define G97PL 2 // ECAN0INTB (ECAN-B)
#define G98PL 4 // ECAN1INTB (ECAN-B)
#define G101PL 0 // reserved
#define G102PL 0 // reserved
#define G103PL 0 // reserved
#define G104PL 0 // reserved
#define G105PL 0 // reserved
#define G106PL 0 // reserved
#define G107PL 0 // reserved
#define G108PL 0 // reserved
#define G111PL 0 // reserved
#define G112PL 0 // reserved
#define G113PL 0 // reserved
#define G114PL 0 // reserved
#define G115PL 0 // reserved
#define G116PL 0 // reserved
#define G117PL 0 // reserved
#define G118PL 0 // reserved
#define G121PL 5 // XINT3 (External)
#define G122PL 3 // XINT4 (External)
#define G123PL 2 // XINT5 (External)
#define G124PL 2 // XINT6 (External)
#define G125PL 1 // XINT7 (External)
#define G126PL 0 // reserved
#define G127PL 6 // LVF (FPA32)
#define G128PL 1 // LUF (FPA32)
// There should be no need to modify code below this line
//-------------------------------------------------------------------------------
// Automatically generate IER interrupt masks MINT1 to MINT16:
//
// Beginning of MINT1:
#if (INT1PL == 0)
#define MINT1_1PL ~(1 << 0)
#else
#define MINT1_1PL 0xFFFF
#endif
#if (INT2PL >= INT1PL) || (INT2PL == 0)
#define MINT1_2PL ~(1 << 1)
#else
#define MINT1_2PL 0xFFFF
#endif
#if (INT3PL >= INT1PL) || (INT3PL == 0)
#define MINT1_3PL ~(1 << 2)
#else
#define MINT1_3PL 0xFFFF
#endif
#if (INT4PL >= INT1PL) || (INT4PL == 0)
#define MINT1_4PL ~(1 << 3)
#else
#define MINT1_4PL 0xFFFF
#endif
#if (INT5PL >= INT1PL) || (INT5PL == 0)
#define MINT1_5PL ~(1 << 4)
#else
#define MINT1_5PL 0xFFFF
#endif
#if (INT6PL >= INT1PL) || (INT6PL == 0)
#define MINT1_6PL ~(1 << 5)
#else
#define MINT1_6PL 0xFFFF
#endif
#if (INT7PL >= INT1PL) || (INT7PL == 0)
#define MINT1_7PL ~(1 << 6)
#else
#define MINT1_7PL 0xFFFF
#endif
#if (INT8PL >= INT1PL) || (INT8PL == 0)
#define MINT1_8PL ~(1 << 7)
#else
#define MINT1_8PL 0xFFFF
#endif
#if (INT9PL >= INT1PL) || (INT9PL == 0)
#define MINT1_9PL ~(1 << 8)
#else
#define MINT1_9PL 0xFFFF
#endif
#if (INT10PL >= INT1PL) || (INT10PL == 0)
#define MINT1_10PL ~(1 << 9)
#else
#define MINT1_10PL 0xFFFF
#endif
#if (INT11PL >= INT1PL) || (INT11PL == 0)
#define MINT1_11PL ~(1 << 10)
#else
#define MINT1_11PL 0xFFFF
#endif
#if (INT12PL >= INT1PL) || (INT12PL == 0)
#define MINT1_12PL ~(1 << 11)
#else
#define MINT1_12PL 0xFFFF
#endif
#if (INT13PL >= INT1PL) || (INT13PL == 0)
#define MINT1_13PL ~(1 << 12)
#else
#define MINT1_13PL 0xFFFF
#endif
#if (INT14PL >= INT1PL) || (INT14PL == 0)
#define MINT1_14PL ~(1 << 13)
#else
#define MINT1_14PL 0xFFFF
#endif
#if (INT15PL >= INT1PL) || (INT15PL == 0)
#define MINT1_15PL ~(1 << 14)
#else
#define MINT1_15PL 0xFFFF
#endif
#if (INT16PL >= INT1PL) || (INT16PL == 0)
#define MINT1_16PL ~(1 << 15)
#else
#define MINT1_16PL 0xFFFF
#endif
#define MINT1 (MINT1_1PL & MINT1_2PL & MINT1_3PL & MINT1_4PL & \
MINT1_5PL & MINT1_6PL & MINT1_7PL & MINT1_8PL & \
MINT1_9PL & MINT1_10PL & MINT1_11PL & MINT1_12PL & \
MINT1_13PL & MINT1_14PL & MINT1_15PL & MINT1_16PL)
// End Of MINT1.
// Beginning of MINT2:
#if (INT1PL >= INT2PL) || (INT1PL == 0)
#define MINT2_1PL ~(1 << 0)
#else
#define MINT2_1PL 0xFFFF
#endif
#if (INT2PL == 0)
#define MINT2_2PL ~(1 << 1)
#else
#define MINT2_2PL 0xFFFF
#endif
#if (INT3PL >= INT2PL) || (INT3PL == 0)
#define MINT2_3PL ~(1 << 2)
#else
#define MINT2_3PL 0xFFFF
#endif
#if (INT4PL >= INT2PL) || (INT4PL == 0)
#define MINT2_4PL ~(1 << 3)
#else
#define MINT2_4PL 0xFFFF
#endif
#if (INT5PL >= INT2PL) || (INT5PL == 0)
#define MINT2_5PL ~(1 << 4)
#else
#define MINT2_5PL 0xFFFF
#endif
#if (INT6PL >= INT2PL) || (INT6PL == 0)
#define MINT2_6PL ~(1 << 5)
#else
#define MINT2_6PL 0xFFFF
#endif
#if (INT7PL >= INT2PL) || (INT7PL == 0)
#define MINT2_7PL ~(1 << 6)
#else
#define MINT2_7PL 0xFFFF
#endif
#if (INT8PL >= INT2PL) || (INT8PL == 0)
#define MINT2_8PL ~(1 << 7)
#else
#define MINT2_8PL 0xFFFF
#endif
#if (INT9PL >= INT2PL) || (INT9PL == 0)
#define MINT2_9PL ~(1 << 8)
#else
#define MINT2_9PL 0xFFFF
#endif
#if (INT10PL >= INT2PL) || (INT10PL == 0)
#define MINT2_10PL ~(1 << 9)
#else
#define MINT2_10PL 0xFFFF
#endif
#if (INT11PL >= INT2PL) || (INT11PL == 0)
#define MINT2_11PL ~(1 << 10)
#else
#define MINT2_11PL 0xFFFF
#endif
#if (INT12PL >= INT2PL) || (INT12PL == 0)
#define MINT2_12PL ~(1 << 11)
#else
#define MINT2_12PL 0xFFFF
#endif
#if (INT13PL >= INT2PL) || (INT13PL == 0)
#define MINT2_13PL ~(1 << 12)
#else
#define MINT2_13PL 0xFFFF
#endif
#if (INT14PL >= INT2PL) || (INT14PL == 0)
#define MINT2_14PL ~(1 << 13)
#else
#define MINT2_14PL 0xFFFF
#endif
#if (INT15PL >= INT2PL) || (INT15PL == 0)
#define MINT2_15PL ~(1 << 14)
#else
#define MINT2_15PL 0xFFFF
#endif
#if (INT16PL >= INT2PL) || (INT16PL == 0)
#define MINT2_16PL ~(1 << 15)
#else
#define MINT2_16PL 0xFFFF
#endif
#define MINT2 (MINT2_1PL & MINT2_2PL & MINT2_3PL & MINT2_4PL & \
MINT2_5PL & MINT2_6PL & MINT2_7PL & MINT2_8PL & \
MINT2_9PL & MINT2_10PL & MINT2_11PL & MINT2_12PL & \
MINT2_13PL & MINT2_14PL & MINT2_15PL & MINT2_16PL)
// End Of MINT2.
// Beginning of MINT3:
#if (INT1PL >= INT3PL) || (INT1PL == 0)
#define MINT3_1PL ~(1 << 0)
#else
#define MINT3_1PL 0xFFFF
#endif
#if (INT2PL >= INT3PL) || (INT2PL == 0)
#define MINT3_2PL ~(1 << 1)
#else
#define MINT3_2PL 0xFFFF
#endif
#if (INT3PL == 0)
#define MINT3_3PL ~(1 << 2)
#else
#define MINT3_3PL 0xFFFF
#endif
#if (INT4PL >= INT3PL) || (INT4PL == 0)
#define MINT3_4PL ~(1 << 3)
#else
#define MINT3_4PL 0xFFFF
#endif
#if (INT5PL >= INT3PL) || (INT5PL == 0)
#define MINT3_5PL ~(1 << 4)
#else
#define MINT3_5PL 0xFFFF
#endif
#if (INT6PL >= INT3PL) || (INT6PL == 0)
#define MINT3_6PL ~(1 << 5)
#else
#define MINT3_6PL 0xFFFF
#endif
#if (INT7PL >= INT3PL) || (INT7PL == 0)
#define MINT3_7PL ~(1 << 6)
#else
#define MINT3_7PL 0xFFFF
#endif
#if (INT8PL >= INT3PL) || (INT8PL == 0)
#define MINT3_8PL ~(1 << 7)
#else
#define MINT3_8PL 0xFFFF
#endif
#if (INT9PL >= INT3PL) || (INT9PL == 0)
#define MINT3_9PL ~(1 << 8)
#else
#define MINT3_9PL 0xFFFF
#endif
#if (INT10PL >= INT3PL) || (INT10PL == 0)
#define MINT3_10PL ~(1 << 9)
#else
#define MINT3_10PL 0xFFFF
#endif
#if (INT11PL >= INT3PL) || (INT11PL == 0)
#define MINT3_11PL ~(1 << 10)
#else
#define MINT3_11PL 0xFFFF
#endif
#if (INT12PL >= INT3PL) || (INT12PL == 0)
#define MINT3_12PL ~(1 << 11)
#else
#define MINT3_12PL 0xFFFF
#endif
#if (INT13PL >= INT3PL) || (INT13PL == 0)
#define MINT3_13PL ~(1 << 12)
#else
#define MINT3_13PL 0xFFFF
#endif
#if (INT14PL >= INT3PL) || (INT14PL == 0)
#define MINT3_14PL ~(1 << 13)
#else
#define MINT3_14PL 0xFFFF
#endif
#if (INT15PL >= INT3PL) || (INT15PL == 0)
#define MINT3_15PL ~(1 << 14)
#else
#define MINT3_15PL 0xFFFF
#endif
#if (INT16PL >= INT3PL) || (INT16PL == 0)
#define MINT3_16PL ~(1 << 15)
#else
#define MINT3_16PL 0xFFFF
#endif
#define MINT3 (MINT3_1PL & MINT3_2PL & MINT3_3PL & MINT3_4PL & \
MINT3_5PL & MINT3_6PL & MINT3_7PL & MINT3_8PL & \
MINT3_9PL & MINT3_10PL & MINT3_11PL & MINT3_12PL & \
MINT3_13PL & MINT3_14PL & MINT3_15PL & MINT3_16PL)
// End Of MINT3.
// Beginning of MINT4:
#if (INT1PL >= INT4PL) || (INT1PL == 0)
#define MINT4_1PL ~(1 << 0)
#else
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