data |= IGP01E1000_PSCFR_SMART_SPEED;			ret_val = phy->ops.write_reg(hw,			                             IGP01E1000_PHY_PORT_CONFIG,			                             data);			if (ret_val)				goto out;		} else if (phy->smart_speed == e1000_smart_speed_off) {			ret_val = phy->ops.read_reg(hw,			                            IGP01E1000_PHY_PORT_CONFIG,			                            &data);			if (ret_val)				goto out;			data &= ~IGP01E1000_PSCFR_SMART_SPEED;			ret_val = phy->ops.write_reg(hw,			                             IGP01E1000_PHY_PORT_CONFIG,			                             data);			if (ret_val)				goto out;		}	}out:	return ret_val;}/** *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state *  @hw: pointer to the HW structure *  @active: true to enable LPLU, false to disable * *  Sets the LPLU D3 state according to the active flag.  When *  activating LPLU this function also disables smart speed *  and vice versa.  LPLU will not be activated unless the *  device autonegotiation advertisement meets standards of *  either 10 or 10/100 or 10/100/1000 at all duplexes. *  This is a function pointer entry point only called by *  PHY setup routines. **/static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,                                           bool active){	struct e1000_phy_info *phy = &hw->phy;	u32 phy_ctrl;	s32 ret_val = E1000_SUCCESS;	u16 data;	DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");	phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);	if (!active) {		phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;		E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);		/*		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used		 * during Dx states where the power conservation is most		 * important.  During driver activity we should enable		 * SmartSpeed, so performance is maintained.		 */		if (phy->smart_speed == e1000_smart_speed_on) {			ret_val = phy->ops.read_reg(hw,			                            IGP01E1000_PHY_PORT_CONFIG,			                            &data);			if (ret_val)				goto out;			data |= IGP01E1000_PSCFR_SMART_SPEED;			ret_val = phy->ops.write_reg(hw,			                             IGP01E1000_PHY_PORT_CONFIG,			                             data);			if (ret_val)				goto out;		} else if (phy->smart_speed == e1000_smart_speed_off) {			ret_val = phy->ops.read_reg(hw,			                            IGP01E1000_PHY_PORT_CONFIG,			                            &data);			if (ret_val)				goto out;			data &= ~IGP01E1000_PSCFR_SMART_SPEED;			ret_val = phy->ops.write_reg(hw,			                             IGP01E1000_PHY_PORT_CONFIG,			                             data);			if (ret_val)				goto out;		}	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||	           (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||	           (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {		phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;		E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);		/*		 * Call gig speed drop workaround on LPLU before accessing		 * any PHY registers		 */		if ((hw->mac.type == e1000_ich8lan) &&		    (hw->phy.type == e1000_phy_igp_3))			e1000_gig_downshift_workaround_ich8lan(hw);		/* When LPLU is enabled, we should disable SmartSpeed */		ret_val = phy->ops.read_reg(hw,		                            IGP01E1000_PHY_PORT_CONFIG,		                            &data);		if (ret_val)			goto out;		data &= ~IGP01E1000_PSCFR_SMART_SPEED;		ret_val = phy->ops.write_reg(hw,		                             IGP01E1000_PHY_PORT_CONFIG,		                             data);	}out:	return ret_val;}/** *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 *  @hw: pointer to the HW structure *  @bank:  pointer to the variable that returns the active bank * *  Reads signature byte from the NVM using the flash access registers. **/static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank){	s32 ret_val = E1000_SUCCESS;	struct e1000_nvm_info *nvm = &hw->nvm;	/* flash bank size is in words */	u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);	u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;	u8 bank_high_byte = 0;	if (hw->mac.type != e1000_ich10lan) {		if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL)			*bank = 1;		else			*bank = 0;	} else if (hw->dev_spec != NULL) {		/*		 * Make sure the signature for bank 0 is valid,		 * if not check for bank1		 */		e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte);		if ((bank_high_byte & 0xC0) == 0x80) {			*bank = 0;		} else {			/*			 * find if segment 1 is valid by verifying			 * bit 15:14 = 10b in word 0x13			 */			e1000_read_flash_byte_ich8lan(hw,			                              act_offset + bank1_offset,			                              &bank_high_byte);						/* bank1 has a valid signature equivalent to SEC1V */			if ((bank_high_byte & 0xC0) == 0x80) {				*bank = 1;			} else {				DEBUGOUT("ERROR: EEPROM not present\n");				ret_val = -E1000_ERR_NVM;			}		}	} else {		DEBUGOUT("DEV SPEC is NULL\n");		ret_val = -E1000_ERR_NVM;	}		return ret_val;}/** *  e1000_read_nvm_ich8lan - Read word(s) from the NVM *  @hw: pointer to the HW structure *  @offset: The offset (in bytes) of the word(s) to read. *  @words: Size of data to read in words *  @data: Pointer to the word(s) to read at offset. * *  Reads a word(s) from the NVM using the flash access registers. **/static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,                                  u16 *data){	struct e1000_nvm_info *nvm = &hw->nvm;	struct e1000_dev_spec_ich8lan *dev_spec;	u32 act_offset;	s32 ret_val = E1000_SUCCESS;	u32 bank = 0;	u16 i, word;	DEBUGFUNC("e1000_read_nvm_ich8lan");	dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;	if (!dev_spec) {		DEBUGOUT("dev_spec pointer is set to NULL.\n");		ret_val = -E1000_ERR_CONFIG;		goto out;	}	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||	    (words == 0)) {		DEBUGOUT("nvm parameter(s) out of bounds\n");		ret_val = -E1000_ERR_NVM;		goto out;	}	ret_val = nvm->ops.acquire(hw);	if (ret_val)		goto out;	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);	if (ret_val != E1000_SUCCESS)		goto out;	act_offset = (bank) ? nvm->flash_bank_size : 0;	act_offset += offset;	for (i = 0; i < words; i++) {		if ((dev_spec->shadow_ram) &&		    (dev_spec->shadow_ram[offset+i].modified)) {			data[i] = dev_spec->shadow_ram[offset+i].value;		} else {			ret_val = e1000_read_flash_word_ich8lan(hw,			                                        act_offset + i,			                                        &word);			if (ret_val)				break;			data[i] = word;		}	}	nvm->ops.release(hw);out:	return ret_val;}/** *  e1000_flash_cycle_init_ich8lan - Initialize flash *  @hw: pointer to the HW structure * *  This function does initial flash setup so that a new read/write/erase cycle *  can be started. **/static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw){	union ich8_hws_flash_status hsfsts;	s32 ret_val = -E1000_ERR_NVM;	s32 i = 0;	DEBUGFUNC("e1000_flash_cycle_init_ich8lan");	hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);	/* Check if the flash descriptor is valid */	if (hsfsts.hsf_status.fldesvalid == 0) {		DEBUGOUT("Flash descriptor invalid.  "		         "SW Sequencing must be used.");		goto out;	}	/* Clear FCERR and DAEL in hw status by writing 1 */	hsfsts.hsf_status.flcerr = 1;	hsfsts.hsf_status.dael = 1;	E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);	/*	 * Either we should have a hardware SPI cycle in progress	 * bit to check against, in order to start a new cycle or	 * FDONE bit should be changed in the hardware so that it	 * is 1 after hardware reset, which can then be used as an	 * indication whether a cycle is in progress or has been	 * completed.	 */	if (hsfsts.hsf_status.flcinprog == 0) {		/*		 * There is no cycle running at present,		 * so we can start a cycle.		 * Begin by setting Flash Cycle Done.		 */		hsfsts.hsf_status.flcdone = 1;		E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);		ret_val = E1000_SUCCESS;	} else {		/*		 * Otherwise poll for sometime so the current		 * cycle has a chance to end before giving up.		 */		for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {			hsfsts.regval = E1000_READ_FLASH_REG16(hw,			                                      ICH_FLASH_HSFSTS);			if (hsfsts.hsf_status.flcinprog == 0) {				ret_val = E1000_SUCCESS;				break;			}			usec_delay(1);		}		if (ret_val == E1000_SUCCESS) {			/*			 * Successful in waiting for previous cycle to timeout,			 * now set the Flash Cycle Done.			 */			hsfsts.hsf_status.flcdone = 1;			E1000_WRITE_FLASH_REG16(hw,			                        ICH_FLASH_HSFSTS,			                        hsfsts.regval);		} else {			DEBUGOUT("Flash controller busy, cannot get access");		}	}out:	return ret_val;}/** *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) *  @hw: pointer to the HW structure *  @timeout: maximum time to wait for completion * *  This function starts a flash cycle and waits for its completion. **/static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout){	union ich8_hws_flash_ctrl hsflctl;	union ich8_hws_flash_status hsfsts;	s32 ret_val = -E1000_ERR_NVM;	u32 i = 0;	DEBUGFUNC("e1000_flash_cycle_ich8lan");	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */	hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);	hsflctl.hsf_ctrl.flcgo = 1;	E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);	/* wait till FDONE bit is set to 1 */	do {		hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);		if (hsfsts.hsf_status.flcdone == 1)			break;		usec_delay(1);	} while (i++ < timeout);	if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)		ret_val = E1000_SUCCESS;	return ret_val;}/** *  e1000_read_flash_word_ich8lan - Read word from flash *  @hw: pointer to the HW structure *  @offset: offset to data location *  @data: pointer to the location for storing the data * *  Reads the flash word at offset into data.  Offset is converted *  to bytes before read. **/static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,                                         u16 *data){	s32 ret_val;	DEBUGFUNC("e1000_read_flash_word_ich8lan");	if (!data) {		ret_val = -E1000_ERR_NVM;		goto out;	}	/* Must convert offset into bytes. */	offset <<= 1;	ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);out:	return ret_val;}/** *  e1000_read_flash_byte_ich8lan - Read byte from flash *  @hw: pointer to the HW structure *  @offset: The offset of the byte to read. *  @data: Pointer to a byte to store the value read. * *  Reads a single byte from the NVM using the flash access registers. **/static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,                                         u8* data){	s32 ret_val = E1000_SUCCESS;	u16 word = 0;	ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);	if (ret_val)		goto out;	*data = (u8)word;out:	return ret_val;}/** *  e1000_read_flash_data_ich8lan - Read byte or word from NVM *  @hw: pointer to the HW structure *  @offset: The offset (in bytes) of the byte or word to read. *  @size: Size of data to read, 1=byte 2=word *  @data: Pointer to the word to store the value read. * *  Reads a byte or word from the NVM using the flash access registers. **/static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,                                         u8 size, u16* data){	union ich8_hws_flash_status hsfsts;	union ich8_hws_flash_ctrl hsflctl;	u32 flash_linear_addr;	u32 flash_data = 0;	s32 ret_val = -E1000_ERR_NVM;	u8 count = 0;	DEBUGFUNC("e1000_read_flash_data_ich8lan");	if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)		goto out;	flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +	                    hw->nvm.flash_base_addr;	do {		usec_delay(1);		/* Steps */		ret_val = e1000_flash_cycle_init_ich8lan(hw);		if (ret_val != E1000_SUCCESS)			break;		hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */