?? e1000_defines.h
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* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) * o RXSEQ = Receive Sequence Error * o LSC = Link Status Change */#define IMS_ENABLE_MASK ( \ E1000_IMS_RXT0 | \ E1000_IMS_TXDW | \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ | \ E1000_IMS_LSC)/* Interrupt Mask Set */#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW#define E1000_IMS_SRPD E1000_ICR_SRPD#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */#define E1000_IMS_DSW E1000_ICR_DSW#define E1000_IMS_PHYINT E1000_ICR_PHYINT#define E1000_IMS_EPRST E1000_ICR_EPRST#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts *//* Extended Interrupt Mask Set */#define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */#define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */#define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */#define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */#define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */#define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */#define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */#define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */#define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active *//* Interrupt Cause Set */#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW#define E1000_ICS_SRPD E1000_ICR_SRPD#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */#define E1000_ICS_DSW E1000_ICR_DSW#define E1000_ICS_PHYINT E1000_ICR_PHYINT#define E1000_ICS_EPRST E1000_ICR_EPRST/* Extended Interrupt Cause Set */#define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */#define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */#define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */#define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */#define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */#define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */#define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */#define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */#define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */#define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active *//* Transmit Descriptor Control */#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 *//* Enable the counting of descriptors still to be processed. */#define E1000_TXDCTL_COUNT_DESC 0x00400000/* Flow Control Constants */#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100#define FLOW_CONTROL_TYPE 0x8808/* 802.1q VLAN Packet Size */#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) *//* Receive Address *//* * Number of high/low register pairs in the RAR. The RAR (Receive Address * Registers) holds the directed and multicast addresses that we monitor. * Technically, we have 16 spots. However, we reserve one of these spots * (RAR[15]) for our directed address used by controllers with * manageability enabled, allowing us room for 15 multicast addresses. */#define E1000_RAR_ENTRIES 15#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid *//* Error Codes */#define E1000_SUCCESS 0#define E1000_ERR_NVM 1#define E1000_ERR_PHY 2#define E1000_ERR_CONFIG 3#define E1000_ERR_PARAM 4#define E1000_ERR_MAC_INIT 5#define E1000_ERR_PHY_TYPE 6#define E1000_ERR_RESET 9#define E1000_ERR_MASTER_REQUESTS_PENDING 10#define E1000_ERR_HOST_INTERFACE_COMMAND 11#define E1000_BLK_PHY_RESET 12#define E1000_ERR_SWFW_SYNC 13#define E1000_NOT_IMPLEMENTED 14/* Loop limit on how long we wait for auto-negotiation to complete */#define FIBER_LINK_UP_LIMIT 50#define COPPER_LINK_UP_LIMIT 10#define PHY_AUTO_NEG_LIMIT 45#define PHY_FORCE_LIMIT 20/* Number of 100 microseconds we wait for PCI Express master disable */#define MASTER_DISABLE_TIMEOUT 800/* Number of milliseconds we wait for PHY configuration done after MAC reset */#define PHY_CFG_TIMEOUT 100/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */#define MDIO_OWNERSHIP_TIMEOUT 10/* Number of milliseconds for NVM auto read done after MAC reset. */#define AUTO_READ_DONE_TIMEOUT 10/* Flow Control */#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission *//* Transmit Configuration Word */#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */#define E1000_TXCW_NP 0x00008000 /* TXCW next page */#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable *//* Receive Configuration Word */#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */#define E1000_RXCW_CC 0x10000000 /* Receive config change */#define E1000_RXCW_C 0x20000000 /* Receive config */#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete *//* PCI Express Control */#define E1000_GCR_RXD_NO_SNOOP 0x00000001#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004#define E1000_GCR_TXD_NO_SNOOP 0x00000008#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ E1000_GCR_RXDSCW_NO_SNOOP | \ E1000_GCR_RXDSCR_NO_SNOOP | \ E1000_GCR_TXD_NO_SNOOP | \ E1000_GCR_TXDSCW_NO_SNOOP | \ E1000_GCR_TXDSCR_NO_SNOOP)/* PHY Control Register */#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */#define MII_CR_POWER_DOWN 0x0800 /* Power down */#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */#define MII_CR_SPEED_1000 0x0040#define MII_CR_SPEED_100 0x2000#define MII_CR_SPEED_10 0x0000/* PHY Status Register */#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable *//* Autoneg Advertisement Register */#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported *//* Link Partner Ability Register (Base Page) */#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable 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