/*******************************************************************************  Intel PRO/1000 Linux driver  Copyright(c) 1999 - 2008 Intel Corporation.  This program is free software; you can redistribute it and/or modify it  under the terms and conditions of the GNU General Public License,  version 2, as published by the Free Software Foundation.  This program is distributed in the hope it will be useful, but WITHOUT  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for  more details.  You should have received a copy of the GNU General Public License along with  this program; if not, write to the Free Software Foundation, Inc.,  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.  The full GNU General Public License is included in this distribution in  the file called "COPYING".  Contact Information:  Linux NICS <linux.nics@intel.com>  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497*******************************************************************************/#ifndef _E1000_REGS_H_#define _E1000_REGS_H_#define E1000_CTRL     0x00000  /* Device Control - RW */#define E1000_CTRL_DUP 0x00004  /* Device Control Duplicate (Shadow) - RW */#define E1000_STATUS   0x00008  /* Device Status - RO */#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */#define E1000_EERD     0x00014  /* EEPROM Read - RW */#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */#define E1000_FLA      0x0001C  /* Flash Access - RW */#define E1000_MDIC     0x00020  /* MDI Control - RW */#define E1000_SCTL     0x00024  /* SerDes Control - RW */#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */#define E1000_FEXTNVM  0x00028  /* Future Extended NVM - RW */#define E1000_FCT      0x00030  /* Flow Control Type - RW */#define E1000_CONNSW   0x00034  /* Copper/Fiber switch control - RW */#define E1000_VET      0x00038  /* VLAN Ether Type - RW */#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */#define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */#define E1000_IVAR     0x000E4  /* Interrupt Vector Allocation Register - RW */#define E1000_RCTL     0x00100  /* Rx Control - RW */#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */#define E1000_TXCW     0x00178  /* Tx Configuration Word - RW */#define E1000_RXCW     0x00180  /* Rx Configuration Word - RO */#define E1000_EICR     0x01580  /* Ext. Interrupt Cause Read - R/clr */#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))#define E1000_EICS     0x01520  /* Ext. Interrupt Cause Set - W0 */#define E1000_EIMS     0x01524  /* Ext. Interrupt Mask Set/Read - RW */#define E1000_EIMC     0x01528  /* Ext. Interrupt Mask Clear - WO */#define E1000_EIAC     0x0152C  /* Ext. Interrupt Auto Clear - RW */#define E1000_EIAM     0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */#define E1000_TCTL     0x00400  /* Tx Control - RW */#define E1000_TCTL_EXT 0x00404  /* Extended Tx Control - RW */#define E1000_TIPG     0x00410  /* Tx Inter-packet gap -RW */#define E1000_TBT      0x00448  /* Tx Burst Timer - RW */#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */#define E1000_LEDCTL   0x00E00  /* LED Control - RW */#define E1000_EXTCNF_CTRL  0x00F00  /* Extended Configuration Control */#define E1000_EXTCNF_SIZE  0x00F08  /* Extended Configuration Size */#define E1000_PHY_CTRL     0x00F10  /* PHY Control Register in CSR */#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */#define E1000_PBS      0x01008  /* Packet Buffer Size */#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */#define E1000_EEARBC   0x01024  /* EEPROM Auto Read Bus Control */#define E1000_FLASHT   0x01028  /* FLASH Timer Register */#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */#define E1000_FLSWCTL  0x01030  /* FLASH control register */#define E1000_FLSWDATA 0x01034  /* FLASH data register */#define E1000_FLSWCNT  0x01038  /* FLASH Access Counter */#define E1000_FLOP     0x0103C  /* FLASH Opcode Register */#define E1000_I2CCMD   0x01028  /* SFPI2C Command Register - RW */#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */#define E1000_WDSTP    0x01040  /* Watchdog Setup - RW */#define E1000_SWDSTS   0x01044  /* SW Device Status - RW */#define E1000_FRTIMER  0x01048  /* Free Running Timer - RW */#define E1000_TCPTIMER 0x0104C  /* TCP Timer - RW */#define E1000_ERT      0x02008  /* Early Rx Threshold - RW */#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */#define E1000_PSRCTL   0x02170  /* Packet Split Receive Control - RW */#define E1000_RDFPCQ(_n)  (0x02430 + (0x4 * (_n)))#define E1000_PBRTH    0x02458  /* PB Rx Arbitration Threshold - RW */#define E1000_FCRTV    0x02460  /* Flow Control Refresh Timer Value - RW *//* Split and Replication Rx Control - RW */#define E1000_RDPUMB   0x025CC  /* DMA Rx Descriptor uC Mailbox - RW */#define E1000_RDPUAD   0x025D0  /* DMA Rx Descriptor uC Addr Command - RW */#define E1000_RDPUWD   0x025D4  /* DMA Rx Descriptor uC Data Write - RW */#define E1000_RDPURD   0x025D8  /* DMA Rx Descriptor uC Data Read - RW */#define E1000_RDPUCTL  0x025DC  /* DMA Rx Descriptor uC Control - RW */#define E1000_RDTR     0x02820  /* Rx Delay Timer - RW */#define E1000_RADV     0x0282C  /* Rx Interrupt Absolute Delay Timer - RW *//* * Convenience macros * * Note: "_n" is the queue number of the register to be written to. * * Example usage: * E1000_RDBAL_REG(current_rx_queue) */#define E1000_RDBAL(_n)   ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : (0x0C000 + ((_n) * 0x40)))#define E1000_RDBAH(_n)   ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : (0x0C004 + ((_n) * 0x40)))#define E1000_RDLEN(_n)   ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : (0x0C008 + ((_n) * 0x40)))#define E1000_SRRCTL(_n)  ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : (0x0C00C + ((_n) * 0x40)))#define E1000_RDH(_n)     ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : (0x0C010 + ((_n) * 0x40)))#define E1000_RDT(_n)     ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : (0x0C018 + ((_n) * 0x40)))#define E1000_RXDCTL(_n)  ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : (0x0C028 + ((_n) * 0x40)))#define E1000_TDBAL(_n)   ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : (0x0E000 + ((_n) * 0x40)))#define E1000_TDBAH(_n)   ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : (0x0E004 + ((_n) * 0x40)))#define E1000_TDLEN(_n)   ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : (0x0E008 + ((_n) * 0x40)))#define E1000_TDH(_n)     ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : (0x0E010 + ((_n) * 0x40)))#define E1000_TDT(_n)     ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : (0x0E018 + ((_n) * 0x40)))#define E1000_TXDCTL(_n)  ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : (0x0E028 + ((_n) * 0x40)))#define E1000_TARC(_n)    (0x03840 + (_n << 8))#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))#define E1000_TDWBAL(_n)  ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : (0x0E038 + ((_n) * 0x40)))#define E1000_TDWBAH(_n)  ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : (0x0E03C + ((_n) * 0x40)))#define E1000_RSRPD    0x02C00  /* Rx Small Packet Detect - RW */#define E1000_RAID     0x02C08  /* Receive Ack Interrupt Delay - RW */#define E1000_TXDMAC   0x03000  /* Tx DMA Control - RW */#define E1000_KABGTXD  0x03004  /* AFE Band Gap Transmit Ref Data */#define E1000_PSRTYPE(_i)       (0x05480 + ((_i) * 4))#define E1000_RAL(_i)  (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x054E0 + ((_i - 16) * 8)))#define E1000_RAH(_i)  (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x054E4 + ((_i - 16) * 8)))#define E1000_IP4AT_REG(_i)     (0x05840 + ((_i) * 8))#define E1000_IP6AT_REG(_i)     (0x05880 + ((_i) * 4))#define E1000_WUPM_REG(_i)      (0x05A00 + ((_i) * 4))#define E1000_FFMT_REG(_i)      (0x09000 + ((_i) * 8))#define E1000_FFVT_REG(_i)      (0x09800 + ((_i) * 8))#define E1000_FFLT_REG(_i)      (0x05F00 + ((_i) * 8))#define E1000_TDFH     0x03410  /* Tx Data FIFO Head - RW */#define E1000_TDFT     0x03418  /* Tx Data FIFO Tail - RW */#define E1000_TDFHS    0x03420  /* Tx Data FIFO Head Saved - RW */#define E1000_TDFTS    0x03428  /* Tx Data FIFO Tail Saved - RW */#define E1000_TDFPC    0x03430  /* Tx Data FIFO Packet Count - RW */#define E1000_TDPUMB   0x0357C  /* DMA Tx Descriptor uC Mail Box - RW */#define E1000_TDPUAD   0x03580  /* DMA Tx Descriptor uC Addr Command - RW */#define E1000_TDPUWD   0x03584  /* DMA Tx Descriptor uC Data Write - RW */#define E1000_TDPURD   0x03588  /* DMA Tx Descriptor uC Data  Read  - RW */#define E1000_TDPUCTL  0x0358C  /* DMA Tx Descriptor uC Control - RW */#define E1000_DTXCTL   0x03590  /* DMA Tx Control - RW */#define E1000_TIDV     0x03820  /* Tx Interrupt Delay Value - RW */#define E1000_TADV     0x0382C  /* Tx Interrupt Absolute Delay Val - RW */