/*******************************************************************************  Intel PRO/1000 Linux driver  Copyright(c) 1999 - 2008 Intel Corporation.  This program is free software; you can redistribute it and/or modify it  under the terms and conditions of the GNU General Public License,  version 2, as published by the Free Software Foundation.  This program is distributed in the hope it will be useful, but WITHOUT  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for  more details.  You should have received a copy of the GNU General Public License along with  this program; if not, write to the Free Software Foundation, Inc.,  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.  The full GNU General Public License is included in this distribution in  the file called "COPYING".  Contact Information:  Linux NICS <linux.nics@intel.com>  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497*******************************************************************************/#include "e1000_hw.h"/** *  e1000_init_nvm_ops_generic - Initialize NVM function pointers *  @hw: pointer to the HW structure * *  Setups up the function pointers to no-op functions **/void e1000_init_nvm_ops_generic(struct e1000_hw *hw){	struct e1000_nvm_info *nvm = &hw->nvm;	DEBUGFUNC("e1000_init_nvm_ops_generic");	/* Initialize function pointers */	nvm->ops.reload = e1000_reload_nvm_generic;}/** *  e1000_raise_eec_clk - Raise EEPROM clock *  @hw: pointer to the HW structure *  @eecd: pointer to the EEPROM * *  Enable/Raise the EEPROM clock bit. **/static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd){	*eecd = *eecd | E1000_EECD_SK;	E1000_WRITE_REG(hw, E1000_EECD, *eecd);	E1000_WRITE_FLUSH(hw);	usec_delay(hw->nvm.delay_usec);}/** *  e1000_lower_eec_clk - Lower EEPROM clock *  @hw: pointer to the HW structure *  @eecd: pointer to the EEPROM * *  Clear/Lower the EEPROM clock bit. **/static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd){	*eecd = *eecd & ~E1000_EECD_SK;	E1000_WRITE_REG(hw, E1000_EECD, *eecd);	E1000_WRITE_FLUSH(hw);	usec_delay(hw->nvm.delay_usec);}/** *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM *  @hw: pointer to the HW structure *  @data: data to send to the EEPROM *  @count: number of bits to shift out * *  We need to shift 'count' bits out to the EEPROM.  So, the value in the *  "data" parameter will be shifted out to the EEPROM one bit at a time. *  In order to do this, "data" must be broken down into bits. **/static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count){	struct e1000_nvm_info *nvm = &hw->nvm;	u32 eecd = E1000_READ_REG(hw, E1000_EECD);	u32 mask;	DEBUGFUNC("e1000_shift_out_eec_bits");	mask = 0x01 << (count - 1);	if (nvm->type == e1000_nvm_eeprom_microwire)		eecd &= ~E1000_EECD_DO;	else if (nvm->type == e1000_nvm_eeprom_spi)		eecd |= E1000_EECD_DO;	do {		eecd &= ~E1000_EECD_DI;		if (data & mask)			eecd |= E1000_EECD_DI;		E1000_WRITE_REG(hw, E1000_EECD, eecd);		E1000_WRITE_FLUSH(hw);		usec_delay(nvm->delay_usec);		e1000_raise_eec_clk(hw, &eecd);		e1000_lower_eec_clk(hw, &eecd);		mask >>= 1;	} while (mask);	eecd &= ~E1000_EECD_DI;	E1000_WRITE_REG(hw, E1000_EECD, eecd);}/** *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM *  @hw: pointer to the HW structure *  @count: number of bits to shift in * *  In order to read a register from the EEPROM, we need to shift 'count' bits *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to *  the EEPROM (setting the SK bit), and then reading the value of the data out *  "DO" bit.  During this "shifting in" process the data in "DI" bit should *  always be clear. **/static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count){	u32 eecd;	u32 i;	u16 data;	DEBUGFUNC("e1000_shift_in_eec_bits");	eecd = E1000_READ_REG(hw, E1000_EECD);	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);	data = 0;	for (i = 0; i < count; i++) {		data <<= 1;		e1000_raise_eec_clk(hw, &eecd);		eecd = E1000_READ_REG(hw, E1000_EECD);		eecd &= ~E1000_EECD_DI;		if (eecd & E1000_EECD_DO)			data |= 1;		e1000_lower_eec_clk(hw, &eecd);	}	return data;}/** *  e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion *  @hw: pointer to the HW structure *  @ee_reg: EEPROM flag for polling * *  Polls the EEPROM status bit for either read or write completion based *  upon the value of 'ee_reg'. **/s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg){	u32 attempts = 100000;	u32 i, reg = 0;	s32 ret_val = -E1000_ERR_NVM;	DEBUGFUNC("e1000_poll_eerd_eewr_done");	for (i = 0; i < attempts; i++) {		if (ee_reg == E1000_NVM_POLL_READ)			reg = E1000_READ_REG(hw, E1000_EERD);		else			reg = E1000_READ_REG(hw, E1000_EEWR);		if (reg & E1000_NVM_RW_REG_DONE) {			ret_val = E1000_SUCCESS;			break;		}		usec_delay(5);	}	return ret_val;}/** *  e1000_acquire_nvm_generic - Generic request for access to EEPROM *  @hw: pointer to the HW structure * *  Set the EEPROM access request bit and wait for EEPROM access grant bit. *  Return successful if access grant bit set, else clear the request for *  EEPROM access and return -E1000_ERR_NVM (-1). **/s32 e1000_acquire_nvm_generic(struct e1000_hw *hw){	u32 eecd = E1000_READ_REG(hw, E1000_EECD);	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;	s32 ret_val = E1000_SUCCESS;	DEBUGFUNC("e1000_acquire_nvm_generic");	E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);	eecd = E1000_READ_REG(hw, E1000_EECD);	while (timeout) {		if (eecd & E1000_EECD_GNT)			break;		usec_delay(5);		eecd = E1000_READ_REG(hw, E1000_EECD);		timeout--;	}	if (!timeout) {		eecd &= ~E1000_EECD_REQ;		E1000_WRITE_REG(hw, E1000_EECD, eecd);		DEBUGOUT("Could not acquire NVM grant\n");		ret_val = -E1000_ERR_NVM;	}	return ret_val;}/** *  e1000_standby_nvm - Return EEPROM to standby state *  @hw: pointer to the HW structure * *  Return the EEPROM to a standby state. **/static void e1000_standby_nvm(struct e1000_hw *hw){	struct e1000_nvm_info *nvm = &hw->nvm;	u32 eecd = E1000_READ_REG(hw, E1000_EECD);	DEBUGFUNC("e1000_standby_nvm");	if (nvm->type == e1000_nvm_eeprom_microwire) {		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);		E1000_WRITE_REG(hw, E1000_EECD, eecd);		E1000_WRITE_FLUSH(hw);		usec_delay(nvm->delay_usec);		e1000_raise_eec_clk(hw, &eecd);		/* Select EEPROM */		eecd |= E1000_EECD_CS;		E1000_WRITE_REG(hw, E1000_EECD, eecd);		E1000_WRITE_FLUSH(hw);		usec_delay(nvm->delay_usec);		e1000_lower_eec_clk(hw, &eecd);	} else if (nvm->type == e1000_nvm_eeprom_spi) {		/* Toggle CS to flush commands */		eecd |= E1000_EECD_CS;		E1000_WRITE_REG(hw, E1000_EECD, eecd);		E1000_WRITE_FLUSH(hw);		usec_delay(nvm->delay_usec);		eecd &= ~E1000_EECD_CS;		E1000_WRITE_REG(hw, E1000_EECD, eecd);		E1000_WRITE_FLUSH(hw);		usec_delay(nvm->delay_usec);	}}/** *  e1000_stop_nvm - Terminate EEPROM command *  @hw: pointer to the HW structure * *  Terminates the current command by inverting the EEPROM's chip select pin. **/void e1000_stop_nvm(struct e1000_hw *hw){	u32 eecd;	DEBUGFUNC("e1000_stop_nvm");	eecd = E1000_READ_REG(hw, E1000_EECD);	if (hw->nvm.type == e1000_nvm_eeprom_spi) {		/* Pull CS high */		eecd |= E1000_EECD_CS;		e1000_lower_eec_clk(hw, &eecd);	} else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {		/* CS on Microwire is active-high */		eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);		E1000_WRITE_REG(hw, E1000_EECD, eecd);		e1000_raise_eec_clk(hw, &eecd);		e1000_lower_eec_clk(hw, &eecd);	}}/** *  e1000_release_nvm_generic - Release exclusive access to EEPROM *  @hw: pointer to the HW structure * *  Stop any current commands to the EEPROM and clear the EEPROM request bit. **/void e1000_release_nvm_generic(struct e1000_hw *hw){	u32 eecd;	DEBUGFUNC("e1000_release_nvm_generic");	e1000_stop_nvm(hw);	eecd = E1000_READ_REG(hw, E1000_EECD);	eecd &= ~E1000_EECD_REQ;	E1000_WRITE_REG(hw, E1000_EECD, eecd);}/** *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write *  @hw: pointer to the HW structure * *  Setups the EEPROM for reading and writing. **/static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw){	struct e1000_nvm_info *nvm = &hw->nvm;	u32 eecd = E1000_READ_REG(hw, E1000_EECD);	s32 ret_val = E1000_SUCCESS;	u16 timeout = 0;	u8 spi_stat_reg;	DEBUGFUNC("e1000_ready_nvm_eeprom");	if (nvm->type == e1000_nvm_eeprom_microwire) {		/* Clear SK and DI */		eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);		E1000_WRITE_REG(hw, E1000_EECD, eecd);		/* Set CS */		eecd |= E1000_EECD_CS;		E1000_WRITE_REG(hw, E1000_EECD, eecd);	} else if (nvm->type == e1000_nvm_eeprom_spi) {		/* Clear SK and CS */		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);		E1000_WRITE_REG(hw, E1000_EECD, eecd);		usec_delay(1);		timeout = NVM_MAX_RETRY_SPI;		/*		 * Read "Status Register" repeatedly until the LSB is cleared.		 * The EEPROM will signal that the command has been completed		 * by clearing bit 0 of the internal status register.  If it's		 * not cleared within 'timeout', then error out.		 */		while (timeout) {			e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,			                         hw->nvm.opcode_bits);			spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))				break;			usec_delay(5);			e1000_standby_nvm(hw);			timeout--;		}		if (!timeout) {			DEBUGOUT("SPI NVM Status error\n");			ret_val = -E1000_ERR_NVM;			goto out;		}	}out:	return ret_val;}/** *  e1000_read_nvm_spi - Read EEPROM's using SPI *  @hw: pointer to the HW structure *  @offset: offset of word in the EEPROM to read *  @words: number of words to read *  @data: word read from the EEPROM * *  Reads a 16 bit word from the EEPROM. **/s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data){	struct e1000_nvm_info *nvm = &hw->nvm;	u32 i = 0;	s32 ret_val;	u16 word_in;	u8 read_opcode = NVM_READ_OPCODE_SPI;	DEBUGFUNC("e1000_read_nvm_spi");	/*	 * A check for invalid values:  offset too large, too many words,	 * and not enough words.	 */	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||	    (words == 0)) {		DEBUGOUT("nvm parameter(s) out of bounds\n");		ret_val = -E1000_ERR_NVM;		goto out;	}	ret_val = nvm->ops.acquire(hw);	if (ret_val)		goto out;	ret_val = e1000_ready_nvm_eeprom(hw);	if (ret_val)		goto release;	e1000_standby_nvm(hw);	if ((nvm->address_bits == 8) && (offset >= 128))		read_opcode |= NVM_A8_OPCODE_SPI;	/* Send the READ command (opcode + addr) */	e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);	e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);	/*	 * Read the data.  SPI NVMs increment the address with each byte	 * read and will roll over if reading beyond the end.  This allows	 * us to read the whole NVM from any offset	 */	for (i = 0; i < words; i++) {		word_in = e1000_shift_in_eec_bits(hw, 16);		data[i] = (word_in >> 8) | (word_in << 8);	}release:	nvm->ops.release(hw);out:	return ret_val;}