;//     <o1.4..7>   Write Wait States <0-15>
;//                 <i> Number of Wait States added for WS
;//   </e>
XM2CON_Val      EQU     0x00000000
XM2PAR_Val      EQU     0x000070FF

;//   <e.0>  Enable Memory Region 3
;//     <o.1>       Data Bus Width  <0=> 8-bit  <1=> 16-bit
;//     <o1.11>     Enable Dynamic Addressing
;//     <o1.15>     Byte Enabled Write Strobe
;//     <o1.10>     Disable extra Address Latch Hold Cycle
;//     <o1.8>      Disable extra Write Address Hold Cycle
;//     <o1.9>      Disable Read Bus Turn Cycle
;//     <o1.12..14> Address Wait States <0-7>
;//                 <i> Number of Wait States added for AE
;//     <o1.0..3>   Read Wait States <0-15>
;//                 <i> Number of Wait States added for RS
;//     <o1.4..7>   Write Wait States <0-15>
;//                 <i> Number of Wait States added for WS
;//   </e>
XM3CON_Val      EQU     0x00000000
XM3PAR_Val      EQU     0x000070FF

;//   <e.0>         Memory Muxed Mode
XMCFG_Val       EQU     0x00000001
;//   </e>

;// </e>


                PRESERVE8
                

; Area Definition and Entry Point
;  Startup Code must be linked first at Address at which it expects to run.

                AREA    Reset, CODE, READONLY
                ARM


; Exception Vectors
;  Mapped to Address 0.
;  Absolute addressing mode must be used.
;  Dummy Handlers are implemented as infinite loops which can be modified.

Vectors         LDR     PC, Reset_Addr         
                LDR     PC, Undef_Addr
                LDR     PC, SWI_Addr
                LDR     PC, PAbt_Addr
                LDR     PC, DAbt_Addr
                NOP                            ; Reserved Vector 
                LDR     PC, IRQ_Addr
                LDR     PC, FIQ_Addr

                EXTERN Undef_Handler
                EXTERN SWI_Handler
                EXTERN PAbt_Handler
                EXTERN DAbt_Handler
                EXTERN IRQ_Handler
                EXTERN FIQ_Handler

Reset_Addr      DCD     Reset_Handler
Undef_Addr      DCD     Undef_Handler
SWI_Addr        DCD     SWI_Handler
PAbt_Addr       DCD     PAbt_Handler
DAbt_Addr       DCD     DAbt_Handler
                DCD     0                      ; Reserved Address 
IRQ_Addr        DCD     IRQ_Handler
FIQ_Addr        DCD     FIQ_Handler


; Reset Handler

                EXPORT  Reset_Handler
Reset_Handler   


; Setup PLL
                IF      PLL_SETUP <> 0
                LDR     R0, =MMR_BASE
                MOV     R1, #0x01         
                STR     R1, [R0,#POWKEY1_OFFSET]          
                MOV     R1, #PLLCFG_Val      
                STR     R1, [R0,#POWCON_OFFSET]    
                MOV     R1, #0xF4
                STR     R1, [R0,#POWKEY2_OFFSET]
                ENDIF   ; PLL_SETUP


; Setup Pins
                IF      GPIO_SETUP <> 0

                ADR     R10, GPIO_CFG          ; Pointer to GPIO CFG
                LDMIA   R10, {R0-R5}           ; Load GPIO Configuration
                STMIA   R0, {R1-R5}            ; Store GPxCON
                B       GPIO_END

GPIO_CFG        DCD     GPIOBASE
                DCD     GP0CON_Val
                DCD     GP1CON_Val
                DCD     GP2CON_Val
                DCD     GP3CON_Val
                DCD     GP4CON_Val
GPIO_END 

                ENDIF   ; GPIO_SETUP


; Setup External Memory Interface
                IF      XM_SETUP <> 0

                ADR     R10, XM_CFG            ; Pointer to XM CFG
                LDMIA   R10, {R0-R9}           ; Load XM Configuration
                STR     R1, [R0],#0x10         ; Store XMCFG
                STMIA   R0, {R2-R9}            ; Store XMxCON & XMxPAR
                B       XM_END

XM_CFG          DCD     XMBASE
                DCD     XMCFG_Val
                DCD     XM0CON_Val
                DCD     XM1CON_Val
                DCD     XM2CON_Val
                DCD     XM3CON_Val
                DCD     XM0PAR_Val
                DCD     XM1PAR_Val
                DCD     XM2PAR_Val
                DCD     XM3PAR_Val
XM_END

                ENDIF   ; XM_SETUP


; Copy Exception Vectors to Internal RAM and Remap Memory
;  (when Interrupt Vectors are in RAM)
									   
                IF      :DEF:RAM_INTVEC
                ADR     R8, Vectors         ; Source
                LDR     R9, =0x00010000     ; Destination
                LDMIA   R8!, {R0-R7}        ; Load Vectors 
                STMIA   R9!, {R0-R7}        ; Store Vectors 
                LDMIA   R8!, {R0-R7}        ; Load Handler Addresses 
                STMIA   R9!, {R0-R7}        ; Store Handler Addresses 
                LDR     R0, =MMR_BASE
                MOV     R1, #1     
                STR     R1, [R0,#REMAP_OFFSET]          
                ENDIF


; Setup Stack for each mode

                LDR     R0, =Stack_Top

;  Enter Undefined Instruction Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #UND_Stack_Size

;  Enter Abort Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #ABT_Stack_Size

;  Enter FIQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #FIQ_Stack_Size

;  Enter IRQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #IRQ_Stack_Size

;  Enter Supervisor Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #SVC_Stack_Size

;  Enter User Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_USR
                MOV     SP, R0
                SUB     SL, SP, #USR_Stack_Size


; Enter the C code

                IMPORT  main
                LDR     R0, =main
                BX      R0


; User Initial Stack & Heap
                AREA    |.text|, CODE, READONLY

                IMPORT  __use_two_region_memory
                EXPORT  __user_initial_stackheap
__user_initial_stackheap

                LDR     R0, =  Heap_Mem
                LDR     R1, =(Stack_Mem + USR_Stack_Size)
                LDR     R2, = (Heap_Mem +      Heap_Size)
                LDR     R3, = Stack_Mem
                BX      LR


                END