<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SPI_RXBUFF"></a><b>SPI_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_RXBUFF">AT91C_SPI_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SPI_TXBUFE"></a><b>SPI_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_TXBUFE">AT91C_SPI_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="SPI_NSSR"></a><b>SPI_NSSR</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_NSSR">AT91C_SPI_NSSR</a></font></td><td><b>NSSR Interrupt</b><br>0 = No rising edge detected on NSS pin since last read.<br>1 = A rising edge occured on NSS pin since last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="SPI_TXEMPTY"></a><b>SPI_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_TXEMPTY">AT91C_SPI_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>As soon as a data is written in the SPI_TDR.<br>The SPI_TDR register and internal shifter are empty.<br>If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.</td></tr>
</null></table>
<a name="SPI_IMR"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> SPI_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7S64_h.html#AT91C_SPI_IMR">AT91C_SPI_IMR</a></i> 0xFFFE001C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SPI_RDRF"></a><b>SPI_RDRF</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_RDRF">AT91C_SPI_RDRF</a></font></td><td><b>Receive Data Register Full</b><br>0 = No data has been received since the last read of SPI_RDR<br>1= Data has been received and the received data has been transferred from the serializer to SPI_RDR since the lastread of SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SPI_TDRE"></a><b>SPI_TDRE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_TDRE">AT91C_SPI_TDRE</a></font></td><td><b>Transmit Data Register Empty</b><br>0 = Data has been written to SPI_TDR and not yet transferred to the serializer.<br>1 = The last data written in the Transmit Data Register has been transferred in the serializer.<br>TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SPI_MODF"></a><b>SPI_MODF</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_MODF">AT91C_SPI_MODF</a></font></td><td><b>Mode Fault Error</b><br>0 = No Mode Fault has been detected since the last read of SPI_SR.<br>1 = A Mode Fault occurred since the last read of the SPI_SR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SPI_OVRES"></a><b>SPI_OVRES</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_OVRES">AT91C_SPI_OVRES</a></font></td><td><b>Overrun Error Status</b><br>0 = No overrun has been detected since the last read of SPI_SR.<br>1 = An overrun has occurred since the last read of SPI_SR.<br>An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SPI_ENDRX"></a><b>SPI_ENDRX</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_ENDRX">AT91C_SPI_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SPI_ENDTX"></a><b>SPI_ENDTX</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_ENDTX">AT91C_SPI_ENDTX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SPI_RXBUFF"></a><b>SPI_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_RXBUFF">AT91C_SPI_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SPI_TXBUFE"></a><b>SPI_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_TXBUFE">AT91C_SPI_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="SPI_NSSR"></a><b>SPI_NSSR</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_NSSR">AT91C_SPI_NSSR</a></font></td><td><b>NSSR Interrupt</b><br>0 = No rising edge detected on NSS pin since last read.<br>1 = A rising edge occured on NSS pin since last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="SPI_TXEMPTY"></a><b>SPI_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_TXEMPTY">AT91C_SPI_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>As soon as a data is written in the SPI_TDR.<br>The SPI_TDR register and internal shifter are empty.<br>If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.</td></tr>
</null></table>
<a name="SPI_CSR"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> SPI_CSR  <i>Chip Select Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7S64_h.html#AT91C_SPI_CSR">AT91C_SPI_CSR</a></i> 0xFFFE0030</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SPI_CPOL"></a><b>SPI_CPOL</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_CPOL">AT91C_SPI_CPOL</a></font></td><td><b>Clock Polarity</b><br>0 = The inactive state value of SPCK is logic level zero.<br>1 = The inactive state value of SPCK is logic level one.<br>CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce a desired clock/data relationship between master and slave devices.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SPI_NCPHA"></a><b>SPI_NCPHA</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_NCPHA">AT91C_SPI_NCPHA</a></font></td><td><b>Clock Phase</b><br>0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.<br>1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.<br><br>NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce a desired clock/data relationship between master and slave devices.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SPI_CSAAT"></a><b>SPI_CSAAT</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_CSAAT">AT91C_SPI_CSAAT</a></font></td><td><b>Chip Select Active After Transfer</b><br>0 = The PCS Line raises at soon as the last transfer is achieved.<br>1 = The PCS does not raise after the last transfer is acheived. It remains active until a new transfer is requested on a different chip select.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7..4</td><td align="CENTER"><a name="SPI_BITS"></a><b>SPI_BITS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_BITS">AT91C_SPI_BITS</a></font></td><td><b>Bits Per Transfer</b><br>The BITS field determines the number of data bits transferred.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SPI_BITS_8"></a><b>SPI_BITS_8</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_BITS_8">AT91C_SPI_BITS_8</a></font></td><td><br>8 Bits Per transfer</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SPI_BITS_9"></a><b>SPI_BITS_9</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_BITS_9">AT91C_SPI_BITS_9</a></font></td><td><br>9 Bits Per transfer</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SPI_BITS_10"></a><b>SPI_BITS_10</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_BITS_10">AT91C_SPI_BITS_10</a></font></td><td><br>10 Bits Per transfer</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="SPI_BITS_11"></a><b>SPI_BITS_11</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_BITS_11">AT91C_SPI_BITS_11</a></font></td><td><br>11 Bits Per transfer</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="SPI_BITS_12"></a><b>SPI_BITS_12</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_BITS_12">AT91C_SPI_BITS_12</a></font></td><td><br>12 Bits Per transfer</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="SPI_BITS_13"></a><b>SPI_BITS_13</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_BITS_13">AT91C_SPI_BITS_13</a></font></td><td><br>13 Bits Per transfer</td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="SPI_BITS_14"></a><b>SPI_BITS_14</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_BITS_14">AT91C_SPI_BITS_14</a></font></td><td><br>14 Bits Per transfer</td></tr>
<tr><td align="CENTER">7</td><td align="CENTER"><a name="SPI_BITS_15"></a><b>SPI_BITS_15</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_BITS_15">AT91C_SPI_BITS_15</a></font></td><td><br>15 Bits Per transfer</td></tr>
<tr><td align="CENTER">8</td><td align="CENTER"><a name="SPI_BITS_16"></a><b>SPI_BITS_16</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_BITS_16">AT91C_SPI_BITS_16</a></font></td><td><br>16 Bits Per transfer</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..8</td><td align="CENTER"><a name="SPI_SCBR"></a><b>SPI_SCBR</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_SCBR">AT91C_SPI_SCBR</a></font></td><td><b>Serial Clock Baud Rate</b><br>In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the SPI Master Clock(selected between MCK and MCK/32). The baud rate is selected by writing a value from 2 to 255 in the field SCBR. The following equation determines the SPCK baud rate:<br>	SPCK_Baud_Rate = SPI_Master_Clock_frequency /SCBR<br>Giving SCBR a value of zero or one disables the baud rate generator. SPCK is disabled and assumes its inactive state value. No serial transfers may occur. At reset, baud rate is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">23..16</td><td align="CENTER"><a name="SPI_DLYBS"></a><b>SPI_DLYBS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_DLYBS">AT91C_SPI_DLYBS</a></font></td><td><b>Delay Before SPCK</b><br>This field defines the delay from NPCS valid to the first valid SPCK transition.<br>When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.<br>Otherwise, the following equation determines the delay:<br>NPCS_to_SPCK_Delay = DLYBS / MCK</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31..24</td><td align="CENTER"><a name="SPI_DLYBCT"></a><b>SPI_DLYBCT</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SPI_DLYBCT">AT91C_SPI_DLYBCT</a></font></td><td><b>Delay Between Consecutive Transfers</b><br>This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed.<br>When DLYBCT equals zero, a delay of four SPI Master Clock periods are inserted.<br>Otherwise, the following equation determines the delay:<br>Delay_Between_Consecutive_Transfer = (64 * DLYBCT + SCBR) / (2*MCK)</td></tr>
</null></table>
<a name="SPI_PDC"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7S64_h.html#AT91S_PDC">AT91S_PDC</a></i> SPI_PDC  <i>PDC interface</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="#AT91C_SPI_SPI">AT91C_SPI_SPI</a></i> 0xFFFE0100</font></null></ul></null><hr></html>