<tr><td align="CENTER">4</td><td align="CENTER"><a name="SSC_START_FALL_RF"></a><b>SSC_START_FALL_RF</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_START_FALL_RF">AT91C_SSC_START_FALL_RF</a></font></td><td><br>Detection of a falling edge on RF input</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="SSC_START_RISE_RF"></a><b>SSC_START_RISE_RF</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_START_RISE_RF">AT91C_SSC_START_RISE_RF</a></font></td><td><br>Detection of a rising edge on RF input</td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="SSC_START_LEVEL_RF"></a><b>SSC_START_LEVEL_RF</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_START_LEVEL_RF">AT91C_SSC_START_LEVEL_RF</a></font></td><td><br>Detection of any level change on RF input</td></tr>
<tr><td align="CENTER">7</td><td align="CENTER"><a name="SSC_START_EDGE_RF"></a><b>SSC_START_EDGE_RF</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_START_EDGE_RF">AT91C_SSC_START_EDGE_RF</a></font></td><td><br>Detection of any edge on RF input</td></tr>
<tr><td align="CENTER">8</td><td align="CENTER"><a name="SSC_START_0"></a><b>SSC_START_0</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_START_0">AT91C_SSC_START_0</a></font></td><td><br>Compare 0</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">23..16</td><td align="CENTER"><a name="SSC_STTDLY"></a><b>SSC_STTDLY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_STTDLY">AT91C_SSC_STTDLY</a></font></td><td><b>Receive/Transmit Start Delay</b><br>If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception/transmission.<br>When the Receiver/Transmitter is programmed to start synchronously with the Transmitter/Receiver, the delay is also applied.<br>Please Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive/Transmit Sync Data) reception.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31..24</td><td align="CENTER"><a name="SSC_PERIOD"></a><b>SSC_PERIOD</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_PERIOD">AT91C_SSC_PERIOD</a></font></td><td><b>Receive/Transmit Period Divider Selection</b><br>This field selects the divider to apply to the selected Receive/Transmit Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive/Transmit Clock.</td></tr>
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<a name="SSC_RFMR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> SSC_RFMR  <i>Receive Frame Mode Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S64_h.html#AT91C_SSC_RFMR">AT91C_SSC_RFMR</a></i> 0xFFFD4014</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">4..0</td><td align="CENTER"><a name="SSC_DATLEN"></a><b>SSC_DATLEN</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_DATLEN">AT91C_SSC_DATLEN</a></font></td><td><b>Data Length</b><br>The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver/Transmitter. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_LOOP"></a><b>SSC_LOOP</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_LOOP">AT91C_SSC_LOOP</a></font></td><td><b>Loop Mode</b><br>0: Normal operating mode.<br>1: RD is driven by TD, RF is driven by TF and TK drives RK.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SSC_MSBF"></a><b>SSC_MSBF</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_MSBF">AT91C_SSC_MSBF</a></font></td><td><b>Most Significant Bit First</b><br>0: The lowest significant bit of the data register is sampled first in the bit stream.<br>1: The most significant bit of the data register is sampled first in the bit stream.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11..8</td><td align="CENTER"><a name="SSC_DATNB"></a><b>SSC_DATNB</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_DATNB">AT91C_SSC_DATNB</a></font></td><td><b>Data Number per Frame</b><br>This field defines the number of data words to be received/transfered after each transfer start. If 0, only 1 data word is transferred. Up to 16 data words can be transferred.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19..16</td><td align="CENTER"><a name="SSC_FSLEN"></a><b>SSC_FSLEN</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_FSLEN">AT91C_SSC_FSLEN</a></font></td><td><b>Receive/Transmit Frame Sync length</b><br>Receive:<br>This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. If 0, the Receive Frame Sync Sig-nal is generated during one Receive Clock period and up to a 16-clock period pulse length is possible.<br>Transmit:<br>This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. If 0, the Transmit Frame Sync signal is generated during one Transmit Clock period and up to 16 clock period pulse length is possible.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">22..20</td><td align="CENTER"><a name="SSC_FSOS"></a><b>SSC_FSOS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_FSOS">AT91C_SSC_FSOS</a></font></td><td><b>Receive/Transmit Frame Sync Output Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SSC_FSOS_NONE"></a><b>SSC_FSOS_NONE</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_FSOS_NONE">AT91C_SSC_FSOS_NONE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SSC_FSOS_NEGATIVE"></a><b>SSC_FSOS_NEGATIVE</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_FSOS_NEGATIVE">AT91C_SSC_FSOS_NEGATIVE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Negative Pulse</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SSC_FSOS_POSITIVE"></a><b>SSC_FSOS_POSITIVE</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_FSOS_POSITIVE">AT91C_SSC_FSOS_POSITIVE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Positive Pulse</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="SSC_FSOS_LOW"></a><b>SSC_FSOS_LOW</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_FSOS_LOW">AT91C_SSC_FSOS_LOW</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="SSC_FSOS_HIGH"></a><b>SSC_FSOS_HIGH</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_FSOS_HIGH">AT91C_SSC_FSOS_HIGH</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="SSC_FSOS_TOGGLE"></a><b>SSC_FSOS_TOGGLE</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_FSOS_TOGGLE">AT91C_SSC_FSOS_TOGGLE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">24</td><td align="CENTER"><a name="SSC_FSEDGE"></a><b>SSC_FSEDGE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_FSEDGE">AT91C_SSC_FSEDGE</a></font></td><td><b>Frame Sync Edge Detection</b><br>Determines which edge on Frame Sync will generate the interrupt RXSYN/TXSYN in the SSC Status Register.<br>0: Positive Edge Detection<br>1: Negative Edge Detection</td></tr>
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<a name="SSC_TCMR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> SSC_TCMR  <i>Transmit Clock Mode Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S64_h.html#AT91C_SSC_TCMR">AT91C_SSC_TCMR</a></i> 0xFFFD4018</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">1..0</td><td align="CENTER"><a name="SSC_CKS"></a><b>SSC_CKS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_CKS">AT91C_SSC_CKS</a></font></td><td><b>Receive/Transmit Clock Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SSC_CKS_DIV"></a><b>SSC_CKS_DIV</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_CKS_DIV">AT91C_SSC_CKS_DIV</a></font></td><td><br>Divided Clock</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SSC_CKS_TK"></a><b>SSC_CKS_TK</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_CKS_TK">AT91C_SSC_CKS_TK</a></font></td><td><br>TK Clock signal</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SSC_CKS_RK"></a><b>SSC_CKS_RK</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_CKS_RK">AT91C_SSC_CKS_RK</a></font></td><td><br>RK pin</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">4..2</td><td align="CENTER"><a name="SSC_CKO"></a><b>SSC_CKO</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_CKO">AT91C_SSC_CKO</a></font></td><td><b>Receive/Transmit Clock Output Mode Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SSC_CKO_NONE"></a><b>SSC_CKO_NONE</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_CKO_NONE">AT91C_SSC_CKO_NONE</a></font></td><td><br>Receive/Transmit Clock Output Mode: None RK pin: Input-only</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SSC_CKO_CONTINOUS"></a><b>SSC_CKO_CONTINOUS</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_CKO_CONTINOUS">AT91C_SSC_CKO_CONTINOUS</a></font></td><td><br>Continuous Receive/Transmit Clock RK pin: Output</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SSC_CKO_DATA_TX"></a><b>SSC_CKO_DATA_TX</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_CKO_DATA_TX">AT91C_SSC_CKO_DATA_TX</a></font></td><td><br>Receive/Transmit Clock only during data transfers RK pin: Output</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_CKI"></a><b>SSC_CKI</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_CKI">AT91C_SSC_CKI</a></font></td><td><b>Receive/Transmit Clock Inversion</b><br>0: The data and the Frame Sync signal are sampled on Receive Clock falling edge.<br>1: The data and the Frame Sync signal are shifted out on Receive Clock rising edge.<br>CKI affects only the Receive Clock and not the output clock signal.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11..8</td><td align="CENTER"><a name="SSC_START"></a><b>SSC_START</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_START">AT91C_SSC_START</a></font></td><td><b>Receive/Transmit Start Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SSC_START_CONTINOUS"></a><b>SSC_START_CONTINOUS</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_START_CONTINOUS">AT91C_SSC_START_CONTINOUS</a></font></td><td><br>Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SSC_START_TX"></a><b>SSC_START_TX</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_START_TX">AT91C_SSC_START_TX</a></font></td><td><br>Transmit/Receive start</td></tr>