<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="SSC_TXENA"></a><b>SSC_TXENA</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_TXENA">AT91C_SSC_TXENA</a></font></td><td><b>Transmit Enable</b><br>0: Transmit is disabled.<br>1: Transmit is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="SSC_RXENA"></a><b>SSC_RXENA</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_RXENA">AT91C_SSC_RXENA</a></font></td><td><b>Receive Enable</b><br>0: Receive is disabled.<br>1: Receive is enabled.</td></tr>
</null></table>
<a name="SSC_IER"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> SSC_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S64_h.html#AT91C_SSC_IER">AT91C_SSC_IER</a></i> 0xFFFD4044</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SSC_TXRDY"></a><b>SSC_TXRDY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_TXRDY">AT91C_SSC_TXRDY</a></font></td><td><b>Transmit Ready</b><br>0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).<br>1: SSC_THR is empty.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SSC_TXEMPTY"></a><b>SSC_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_TXEMPTY">AT91C_SSC_TXEMPTY</a></font></td><td><b>Transmit Empty</b><br>0: Data remains in SSC_THR or is currently transmitted from TSR.<br>1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SSC_ENDTX"></a><b>SSC_ENDTX</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_ENDTX">AT91C_SSC_ENDTX</a></font></td><td><b>End Of Transmission</b><br>0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.<br>1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SSC_TXBUFE"></a><b>SSC_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_TXBUFE">AT91C_SSC_TXBUFE</a></font></td><td><b>Transmit Buffer Empty</b><br>0: SSC_TCR or SSC_TNCR have a value other than 0.<br>1: Both SSC_TCR and SSC_TNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SSC_RXRDY"></a><b>SSC_RXRDY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_RXRDY">AT91C_SSC_RXRDY</a></font></td><td><b>Receive Ready</b><br>0: SSC_RHR is empty.<br>1: Data has been received and loaded in SSC_RHR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_OVRUN"></a><b>SSC_OVRUN</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_OVRUN">AT91C_SSC_OVRUN</a></font></td><td><b>Receive Overrun</b><br>0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.<br>1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SSC_ENDRX"></a><b>SSC_ENDRX</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_ENDRX">AT91C_SSC_ENDRX</a></font></td><td><b>End of Reception</b><br>0: Data is written on the Receive Counter Register or Receive Next Counter Register.<br>1: End of PDC transfer when Receive Counter Register has arrived at zero.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SSC_RXBUFF"></a><b>SSC_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_RXBUFF">AT91C_SSC_RXBUFF</a></font></td><td><b>Receive Buffer Full</b><br>0: SSC_RCR or SSC_RNCR have a value other than 0.<br>1: Both SSC_RCR and SSC_RNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="SSC_TXSYN"></a><b>SSC_TXSYN</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_TXSYN">AT91C_SSC_TXSYN</a></font></td><td><b>Transmit Sync</b><br>0: A Tx Sync has not occurred since the last read of the Status Register.<br>1: A Tx Sync has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="SSC_RXSYN"></a><b>SSC_RXSYN</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_RXSYN">AT91C_SSC_RXSYN</a></font></td><td><b>Receive Sync</b><br>0: A Rx Sync has not occurred since the last read of the Status Register.<br>1: A Rx Sync has occurred since the last read of the Status Register.</td></tr>
</null></table>
<a name="SSC_IDR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> SSC_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S64_h.html#AT91C_SSC_IDR">AT91C_SSC_IDR</a></i> 0xFFFD4048</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SSC_TXRDY"></a><b>SSC_TXRDY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_TXRDY">AT91C_SSC_TXRDY</a></font></td><td><b>Transmit Ready</b><br>0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).<br>1: SSC_THR is empty.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SSC_TXEMPTY"></a><b>SSC_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_TXEMPTY">AT91C_SSC_TXEMPTY</a></font></td><td><b>Transmit Empty</b><br>0: Data remains in SSC_THR or is currently transmitted from TSR.<br>1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SSC_ENDTX"></a><b>SSC_ENDTX</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_ENDTX">AT91C_SSC_ENDTX</a></font></td><td><b>End Of Transmission</b><br>0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.<br>1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SSC_TXBUFE"></a><b>SSC_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_TXBUFE">AT91C_SSC_TXBUFE</a></font></td><td><b>Transmit Buffer Empty</b><br>0: SSC_TCR or SSC_TNCR have a value other than 0.<br>1: Both SSC_TCR and SSC_TNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SSC_RXRDY"></a><b>SSC_RXRDY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_RXRDY">AT91C_SSC_RXRDY</a></font></td><td><b>Receive Ready</b><br>0: SSC_RHR is empty.<br>1: Data has been received and loaded in SSC_RHR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_OVRUN"></a><b>SSC_OVRUN</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_OVRUN">AT91C_SSC_OVRUN</a></font></td><td><b>Receive Overrun</b><br>0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.<br>1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SSC_ENDRX"></a><b>SSC_ENDRX</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_ENDRX">AT91C_SSC_ENDRX</a></font></td><td><b>End of Reception</b><br>0: Data is written on the Receive Counter Register or Receive Next Counter Register.<br>1: End of PDC transfer when Receive Counter Register has arrived at zero.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SSC_RXBUFF"></a><b>SSC_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_RXBUFF">AT91C_SSC_RXBUFF</a></font></td><td><b>Receive Buffer Full</b><br>0: SSC_RCR or SSC_RNCR have a value other than 0.<br>1: Both SSC_RCR and SSC_RNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="SSC_TXSYN"></a><b>SSC_TXSYN</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_TXSYN">AT91C_SSC_TXSYN</a></font></td><td><b>Transmit Sync</b><br>0: A Tx Sync has not occurred since the last read of the Status Register.<br>1: A Tx Sync has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="SSC_RXSYN"></a><b>SSC_RXSYN</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_RXSYN">AT91C_SSC_RXSYN</a></font></td><td><b>Receive Sync</b><br>0: A Rx Sync has not occurred since the last read of the Status Register.<br>1: A Rx Sync has occurred since the last read of the Status Register.</td></tr>
</null></table>
<a name="SSC_IMR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> SSC_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S64_h.html#AT91C_SSC_IMR">AT91C_SSC_IMR</a></i> 0xFFFD404C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SSC_TXRDY"></a><b>SSC_TXRDY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_TXRDY">AT91C_SSC_TXRDY</a></font></td><td><b>Transmit Ready</b><br>0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).<br>1: SSC_THR is empty.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SSC_TXEMPTY"></a><b>SSC_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_TXEMPTY">AT91C_SSC_TXEMPTY</a></font></td><td><b>Transmit Empty</b><br>0: Data remains in SSC_THR or is currently transmitted from TSR.<br>1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SSC_ENDTX"></a><b>SSC_ENDTX</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_ENDTX">AT91C_SSC_ENDTX</a></font></td><td><b>End Of Transmission</b><br>0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.<br>1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SSC_TXBUFE"></a><b>SSC_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_TXBUFE">AT91C_SSC_TXBUFE</a></font></td><td><b>Transmit Buffer Empty</b><br>0: SSC_TCR or SSC_TNCR have a value other than 0.<br>1: Both SSC_TCR and SSC_TNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SSC_RXRDY"></a><b>SSC_RXRDY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_RXRDY">AT91C_SSC_RXRDY</a></font></td><td><b>Receive Ready</b><br>0: SSC_RHR is empty.<br>1: Data has been received and loaded in SSC_RHR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_OVRUN"></a><b>SSC_OVRUN</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_OVRUN">AT91C_SSC_OVRUN</a></font></td><td><b>Receive Overrun</b><br>0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.<br>1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SSC_ENDRX"></a><b>SSC_ENDRX</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_ENDRX">AT91C_SSC_ENDRX</a></font></td><td><b>End of Reception</b><br>0: Data is written on the Receive Counter Register or Receive Next Counter Register.<br>1: End of PDC transfer when Receive Counter Register has arrived at zero.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SSC_RXBUFF"></a><b>SSC_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_RXBUFF">AT91C_SSC_RXBUFF</a></font></td><td><b>Receive Buffer Full</b><br>0: SSC_RCR or SSC_RNCR have a value other than 0.<br>1: Both SSC_RCR and SSC_RNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="SSC_TXSYN"></a><b>SSC_TXSYN</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_TXSYN">AT91C_SSC_TXSYN</a></font></td><td><b>Transmit Sync</b><br>0: A Tx Sync has not occurred since the last read of the Status Register.<br>1: A Tx Sync has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="SSC_RXSYN"></a><b>SSC_RXSYN</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_SSC_RXSYN">AT91C_SSC_RXSYN</a></font></td><td><b>Receive Sync</b><br>0: A Rx Sync has not occurred since the last read of the Status Register.<br>1: A Rx Sync has occurred since the last read of the Status Register.</td></tr>
</null></table>
<a name="SSC"></a><h4><a href="AT91SAM7S64_SSC.html#SSC">SSC</a>: <i><a href="AT91SAM7S64_h.html#AT91S_PDC">AT91S_PDC</a></i> SSC  <i>PDC interface</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="#AT91C_SSC_SSC">AT91C_SSC_SSC</a></i> 0xFFFD4100</font></null></ul></null><hr></html>