<tr><td align="CENTER">1</td><td align="CENTER"><a name="TC_BSWTRG_SET"></a><b>TC_BSWTRG_SET</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_TC_BSWTRG_SET">AT91C_TC_BSWTRG_SET</a></font></td><td><br>Effect: set</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="TC_BSWTRG_CLEAR"></a><b>TC_BSWTRG_CLEAR</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_TC_BSWTRG_CLEAR">AT91C_TC_BSWTRG_CLEAR</a></font></td><td><br>Effect: clear</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="TC_BSWTRG_TOGGLE"></a><b>TC_BSWTRG_TOGGLE</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_TC_BSWTRG_TOGGLE">AT91C_TC_BSWTRG_TOGGLE</a></font></td><td><br>Effect: toggle</td></tr>
</null></table></font>
</td></tr>
</null></table>
<a name="TC_CV"></a><h4><a href="#TC">TC</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> TC_CV  <i>Counter Value</i></h4><ul><null><font size="-2"><li><b>TC0</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC0_CV">AT91C_TC0_CV</a></i> 0xFFFA0010</font><font size="-2"><li><b>TC1</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC1_CV">AT91C_TC1_CV</a></i> 0xFFFA0050</font><font size="-2"><li><b>TC2</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC2_CV">AT91C_TC2_CV</a></i> 0xFFFA0090</font></null></ul><br>0-65535 Counter Value contains the counter value in real time.<a name="TC_RA"></a><h4><a href="#TC">TC</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> TC_RA  <i>Register A</i></h4><ul><null><font size="-2"><li><b>TC0</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC0_RA">AT91C_TC0_RA</a></i> 0xFFFA0014</font><font size="-2"><li><b>TC1</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC1_RA">AT91C_TC1_RA</a></i> 0xFFFA0054</font><font size="-2"><li><b>TC2</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC2_RA">AT91C_TC2_RA</a></i> 0xFFFA0094</font></null></ul><br>TC Register A contains the Register A value in real time<a name="TC_RB"></a><h4><a href="#TC">TC</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> TC_RB  <i>Register B</i></h4><ul><null><font size="-2"><li><b>TC0</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC0_RB">AT91C_TC0_RB</a></i> 0xFFFA0018</font><font size="-2"><li><b>TC1</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC1_RB">AT91C_TC1_RB</a></i> 0xFFFA0058</font><font size="-2"><li><b>TC2</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC2_RB">AT91C_TC2_RB</a></i> 0xFFFA0098</font></null></ul><br>TC Register B contains the Register B value in real time<a name="TC_RC"></a><h4><a href="#TC">TC</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> TC_RC  <i>Register C</i></h4><ul><null><font size="-2"><li><b>TC0</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC0_RC">AT91C_TC0_RC</a></i> 0xFFFA001C</font><font size="-2"><li><b>TC1</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC1_RC">AT91C_TC1_RC</a></i> 0xFFFA005C</font><font size="-2"><li><b>TC2</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC2_RC">AT91C_TC2_RC</a></i> 0xFFFA009C</font></null></ul><br>TC Register C contains the Register C value in real time<a name="TC_SR"></a><h4><a href="#TC">TC</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> TC_SR  <i>Status Register</i></h4><ul><null><font size="-2"><li><b>TC0</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC0_SR">AT91C_TC0_SR</a></i> 0xFFFA0020</font><font size="-2"><li><b>TC1</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC1_SR">AT91C_TC1_SR</a></i> 0xFFFA0060</font><font size="-2"><li><b>TC2</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC2_SR">AT91C_TC2_SR</a></i> 0xFFFA00A0</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TC_COVFS"></a><b>TC_COVFS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_COVFS">AT91C_TC_COVFS</a></font></td><td><b>Counter Overflow</b><br>0 = No counter overflow has occurred since the last read of the Status Register.<br>1 = A counter overflow has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TC_LOVRS"></a><b>TC_LOVRS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_LOVRS">AT91C_TC_LOVRS</a></font></td><td><b>Load Overrun</b><br>0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.<br>1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TC_CPAS"></a><b>TC_CPAS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_CPAS">AT91C_TC_CPAS</a></font></td><td><b>RA Compare</b><br>0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.<br>1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TC_CPBS"></a><b>TC_CPBS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_CPBS">AT91C_TC_CPBS</a></font></td><td><b>RB Compare</b><br>0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.<br>1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="TC_CPCS"></a><b>TC_CPCS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_CPCS">AT91C_TC_CPCS</a></font></td><td><b>RC Compare</b><br>0 = RC Compare has not occurred since the last read of the Status Register.<br>1 = RC Compare has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="TC_LDRAS"></a><b>TC_LDRAS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_LDRAS">AT91C_TC_LDRAS</a></font></td><td><b>RA Loading</b><br>0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.<br>1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="TC_LDRBS"></a><b>TC_LDRBS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_LDRBS">AT91C_TC_LDRBS</a></font></td><td><b>RB Loading</b><br>0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.<br>1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="TC_ETRGS"></a><b>TC_ETRGS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_ETRGS">AT91C_TC_ETRGS</a></font></td><td><b>External Trigger</b><br>0 = External trigger has not occurred since the last read of the Status Register.<br>1 = External trigger has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="TC_CLKSTA"></a><b>TC_CLKSTA</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_CLKSTA">AT91C_TC_CLKSTA</a></font></td><td><b>Clock Enabling</b><br>0 = Clock is disabled.<br>1 = Clock is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="TC_MTIOA"></a><b>TC_MTIOA</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_MTIOA">AT91C_TC_MTIOA</a></font></td><td><b>TIOA Mirror</b><br>0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.<br>1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="TC_MTIOB"></a><b>TC_MTIOB</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_MTIOB">AT91C_TC_MTIOB</a></font></td><td><b>TIOA Mirror</b><br>0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low.<br>1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.</td></tr>
</null></table>
<a name="TC_IER"></a><h4><a href="#TC">TC</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> TC_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>TC0</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC0_IER">AT91C_TC0_IER</a></i> 0xFFFA0024</font><font size="-2"><li><b>TC1</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC1_IER">AT91C_TC1_IER</a></i> 0xFFFA0064</font><font size="-2"><li><b>TC2</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC2_IER">AT91C_TC2_IER</a></i> 0xFFFA00A4</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TC_COVFS"></a><b>TC_COVFS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_COVFS">AT91C_TC_COVFS</a></font></td><td><b>Counter Overflow</b><br>0 = No counter overflow has occurred since the last read of the Status Register.<br>1 = A counter overflow has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TC_LOVRS"></a><b>TC_LOVRS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_LOVRS">AT91C_TC_LOVRS</a></font></td><td><b>Load Overrun</b><br>0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.<br>1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TC_CPAS"></a><b>TC_CPAS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_CPAS">AT91C_TC_CPAS</a></font></td><td><b>RA Compare</b><br>0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.<br>1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TC_CPBS"></a><b>TC_CPBS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_CPBS">AT91C_TC_CPBS</a></font></td><td><b>RB Compare</b><br>0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.<br>1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="TC_CPCS"></a><b>TC_CPCS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_CPCS">AT91C_TC_CPCS</a></font></td><td><b>RC Compare</b><br>0 = RC Compare has not occurred since the last read of the Status Register.<br>1 = RC Compare has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="TC_LDRAS"></a><b>TC_LDRAS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_LDRAS">AT91C_TC_LDRAS</a></font></td><td><b>RA Loading</b><br>0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.<br>1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="TC_LDRBS"></a><b>TC_LDRBS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_LDRBS">AT91C_TC_LDRBS</a></font></td><td><b>RB Loading</b><br>0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.<br>1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="TC_ETRGS"></a><b>TC_ETRGS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_ETRGS">AT91C_TC_ETRGS</a></font></td><td><b>External Trigger</b><br>0 = External trigger has not occurred since the last read of the Status Register.<br>1 = External trigger has occurred since the last read of the Status Register.</td></tr>
</null></table>
<a name="TC_IDR"></a><h4><a href="#TC">TC</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> TC_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>TC0</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC0_IDR">AT91C_TC0_IDR</a></i> 0xFFFA0028</font><font size="-2"><li><b>TC1</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC1_IDR">AT91C_TC1_IDR</a></i> 0xFFFA0068</font><font size="-2"><li><b>TC2</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC2_IDR">AT91C_TC2_IDR</a></i> 0xFFFA00A8</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TC_COVFS"></a><b>TC_COVFS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_COVFS">AT91C_TC_COVFS</a></font></td><td><b>Counter Overflow</b><br>0 = No counter overflow has occurred since the last read of the Status Register.<br>1 = A counter overflow has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TC_LOVRS"></a><b>TC_LOVRS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_LOVRS">AT91C_TC_LOVRS</a></font></td><td><b>Load Overrun</b><br>0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.<br>1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TC_CPAS"></a><b>TC_CPAS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_CPAS">AT91C_TC_CPAS</a></font></td><td><b>RA Compare</b><br>0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.<br>1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TC_CPBS"></a><b>TC_CPBS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_CPBS">AT91C_TC_CPBS</a></font></td><td><b>RB Compare</b><br>0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.<br>1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="TC_CPCS"></a><b>TC_CPCS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_CPCS">AT91C_TC_CPCS</a></font></td><td><b>RC Compare</b><br>0 = RC Compare has not occurred since the last read of the Status Register.<br>1 = RC Compare has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="TC_LDRAS"></a><b>TC_LDRAS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_LDRAS">AT91C_TC_LDRAS</a></font></td><td><b>RA Loading</b><br>0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.<br>1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="TC_LDRBS"></a><b>TC_LDRBS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_LDRBS">AT91C_TC_LDRBS</a></font></td><td><b>RB Loading</b><br>0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.<br>1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="TC_ETRGS"></a><b>TC_ETRGS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_ETRGS">AT91C_TC_ETRGS</a></font></td><td><b>External Trigger</b><br>0 = External trigger has not occurred since the last read of the Status Register.<br>1 = External trigger has occurred since the last read of the Status Register.</td></tr>
</null></table>
<a name="TC_IMR"></a><h4><a href="#TC">TC</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> TC_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>TC0</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC0_IMR">AT91C_TC0_IMR</a></i> 0xFFFA002C</font><font size="-2"><li><b>TC1</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC1_IMR">AT91C_TC1_IMR</a></i> 0xFFFA006C</font><font size="-2"><li><b>TC2</b> <i><a href="AT91SAM7S64_h.html#AT91C_TC2_IMR">AT91C_TC2_IMR</a></i> 0xFFFA00AC</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TC_COVFS"></a><b>TC_COVFS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_COVFS">AT91C_TC_COVFS</a></font></td><td><b>Counter Overflow</b><br>0 = No counter overflow has occurred since the last read of the Status Register.<br>1 = A counter overflow has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TC_LOVRS"></a><b>TC_LOVRS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_LOVRS">AT91C_TC_LOVRS</a></font></td><td><b>Load Overrun</b><br>0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.<br>1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TC_CPAS"></a><b>TC_CPAS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_CPAS">AT91C_TC_CPAS</a></font></td><td><b>RA Compare</b><br>0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.<br>1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TC_CPBS"></a><b>TC_CPBS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_CPBS">AT91C_TC_CPBS</a></font></td><td><b>RB Compare</b><br>0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.<br>1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="TC_CPCS"></a><b>TC_CPCS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_CPCS">AT91C_TC_CPCS</a></font></td><td><b>RC Compare</b><br>0 = RC Compare has not occurred since the last read of the Status Register.<br>1 = RC Compare has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="TC_LDRAS"></a><b>TC_LDRAS</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_TC_LDRAS">AT91C_TC_LDRAS</a></font></td><td><b>RA Loading</b><br>0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.<br>1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td>