<tr><td align="CENTER">4</td><td align="CENTER"><a name="US_PAR_NONE"></a><b>US_PAR_NONE</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_US_PAR_NONE">AT91C_US_PAR_NONE</a></font></td><td><br>No Parity</td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="US_PAR_MULTI_DROP"></a><b>US_PAR_MULTI_DROP</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_US_PAR_MULTI_DROP">AT91C_US_PAR_MULTI_DROP</a></font></td><td><br>Multi-drop mode</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">13..12</td><td align="CENTER"><a name="US_NBSTOP"></a><b>US_NBSTOP</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_NBSTOP">AT91C_US_NBSTOP</a></font></td><td><b>Number of Stop bits</b><br>The interpretation of the number of stop bits depends on SYNC.<br>1.5 or 2 stop bits are reserved for the TX function. The RX function uses only the 1 stop bit (there is no check on the 2 stop bit time slot if NBSTOP = 10).<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="US_NBSTOP_1_BIT"></a><b>US_NBSTOP_1_BIT</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_US_NBSTOP_1_BIT">AT91C_US_NBSTOP_1_BIT</a></font></td><td><br>1 stop bit</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_NBSTOP_15_BIT"></a><b>US_NBSTOP_15_BIT</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_US_NBSTOP_15_BIT">AT91C_US_NBSTOP_15_BIT</a></font></td><td><br>Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_NBSTOP_2_BIT"></a><b>US_NBSTOP_2_BIT</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_US_NBSTOP_2_BIT">AT91C_US_NBSTOP_2_BIT</a></font></td><td><br>2 stop bits</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">15..14</td><td align="CENTER"><a name="US_CHMODE"></a><b>US_CHMODE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_CHMODE">AT91C_US_CHMODE</a></font></td><td><b>Channel Mode</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="US_CHMODE_NORMAL"></a><b>US_CHMODE_NORMAL</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_US_CHMODE_NORMAL">AT91C_US_CHMODE_NORMAL</a></font></td><td><br>Normal Mode: The USART channel operates as an RX/TX USART.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_CHMODE_AUTO"></a><b>US_CHMODE_AUTO</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_US_CHMODE_AUTO">AT91C_US_CHMODE_AUTO</a></font></td><td><br>Automatic Echo: Receiver Data Input is connected to the TXD pin.</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_CHMODE_LOCAL"></a><b>US_CHMODE_LOCAL</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_US_CHMODE_LOCAL">AT91C_US_CHMODE_LOCAL</a></font></td><td><br>Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="US_CHMODE_REMOTE"></a><b>US_CHMODE_REMOTE</b><font size="-1"><br><a href="AT91SAM7S64_h.html#AT91C_US_CHMODE_REMOTE">AT91C_US_CHMODE_REMOTE</a></font></td><td><br>Remote Loopback: RXD pin is internally connected to TXD pin.</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="US_MSBF"></a><b>US_MSBF</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_MSBF">AT91C_US_MSBF</a></font></td><td><b>Bit Order</b><br>0 = LSB First<br>1 = MSB First</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="US_MODE9"></a><b>US_MODE9</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_MODE9">AT91C_US_MODE9</a></font></td><td><b>9-bit Character length</b><br>0 = CHRL defines character length.<br>1 = 9-bit character length.<br>MODE9 has priority on character length.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="US_CKLO"></a><b>US_CKLO</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_CKLO">AT91C_US_CKLO</a></font></td><td><b>Clock Output Select</b><br>0 = The USART does not drive the SCK pin.<br>1 = The USART drives the SCK pin if USCLKS[1] is 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="US_OVER"></a><b>US_OVER</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_OVER">AT91C_US_OVER</a></font></td><td><b>Over Sampling Mode</b><br>0 = 16x Oversampling<br>1 = 8x Oversampling</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">20</td><td align="CENTER"><a name="US_INACK"></a><b>US_INACK</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_INACK">AT91C_US_INACK</a></font></td><td><b>Inhibit Non Acknowledge</b><br>0 = The NACK is generated<br>1 = The NACK is not generated<br>Note: This bit will be used only in ISO7816 mode, protocol T = 0 receiver.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">21</td><td align="CENTER"><a name="US_DSNACK"></a><b>US_DSNACK</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_DSNACK">AT91C_US_DSNACK</a></font></td><td><b>Disable Successive NACK</b><br>0 = NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).<br>1 = Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors gener-ate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">24</td><td align="CENTER"><a name="US_MAX_ITER"></a><b>US_MAX_ITER</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_MAX_ITER">AT91C_US_MAX_ITER</a></font></td><td><b>Number of Repetitions</b><br>0-7 This will operate in mode ISO7816, Protocol T=0 only</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">28</td><td align="CENTER"><a name="US_FILTER"></a><b>US_FILTER</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_FILTER">AT91C_US_FILTER</a></font></td><td><b>Receive Line Filter</b><br>0 = The USART does not filter the receive line.<br>1 = The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).</td></tr>
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<a name="US_IER"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> US_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S64_h.html#AT91C_US1_IER">AT91C_US1_IER</a></i> 0xFFFC4008</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S64_h.html#AT91C_US0_IER">AT91C_US0_IER</a></i> 0xFFFC0008</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="US_RXBRK"></a><b>US_RXBRK</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_RXBRK">AT91C_US_RXBRK</a></font></td><td><b>Break Received/End of Break</b><br>0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.<br>1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_TIMEOUT"></a><b>US_TIMEOUT</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_TIMEOUT">AT91C_US_TIMEOUT</a></font></td><td><b>Receiver Time-out</b><br>0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.<br>1 = There has been a time-out since the last Start Time-out command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="US_ITERATION"></a><b>US_ITERATION</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_ITERATION">AT91C_US_ITERATION</a></font></td><td><b>Max number of Repetitions Reached</b><br>Note: This bit will operate only in IS07816 mode, Protocol T = 0.<br>0 = Max number of repetitions has not been reached.<br>1 = Max number of repetitions has been reached.<br>A repetition consists of transmitted characters or successive NACK.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_TXBUFE"></a><b>US_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_TXBUFE">AT91C_US_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_RXBUFF"></a><b>US_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_RXBUFF">AT91C_US_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="US_NACK"></a><b>US_NACK</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_NACK">AT91C_US_NACK</a></font></td><td><b>Non Acknowledge</b><br>0 = A Non Acknowledge has not been detected.<br>1 = A Non Acknowledge has been detected.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="US_RIIC"></a><b>US_RIIC</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_RIIC">AT91C_US_RIIC</a></font></td><td><b>Ring INdicator Input Change Flag</b><br>0 = No input change has been detected on the RI pin since the last read of US_CSR.<br>1 = An input change has been detected on the RI pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="US_DSRIC"></a><b>US_DSRIC</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_DSRIC">AT91C_US_DSRIC</a></font></td><td><b>Data Set Ready Input Change Flag</b><br>0 = No input change has been detected on the DSR pin since the last read of US_CSR.<br>1 = An input change has been detected on the DSR pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="US_DCDIC"></a><b>US_DCDIC</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_DCDIC">AT91C_US_DCDIC</a></font></td><td><b>Data Carrier Flag</b><br>0 = No input change has been detected on the DCD pin since the last read of US_CSR.<br>1 = An input change has been detected on the DCD pin.</td></tr>