<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="US_CTSIC"></a><b>US_CTSIC</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_CTSIC">AT91C_US_CTSIC</a></font></td><td><b>Clear To Send Input Change Flag</b><br>0 = No input change has been detected on the CTS pin since the last read of US_CSR.<br>1 = An input change has been detected on the CTS pin.</td></tr>
</null></table>
<a name="US_IDR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> US_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S64_h.html#AT91C_US1_IDR">AT91C_US1_IDR</a></i> 0xFFFC400C</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S64_h.html#AT91C_US0_IDR">AT91C_US0_IDR</a></i> 0xFFFC000C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="US_RXBRK"></a><b>US_RXBRK</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_RXBRK">AT91C_US_RXBRK</a></font></td><td><b>Break Received/End of Break</b><br>0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.<br>1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_TIMEOUT"></a><b>US_TIMEOUT</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_TIMEOUT">AT91C_US_TIMEOUT</a></font></td><td><b>Receiver Time-out</b><br>0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.<br>1 = There has been a time-out since the last Start Time-out command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="US_ITERATION"></a><b>US_ITERATION</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_ITERATION">AT91C_US_ITERATION</a></font></td><td><b>Max number of Repetitions Reached</b><br>Note: This bit will operate only in IS07816 mode, Protocol T = 0.<br>0 = Max number of repetitions has not been reached.<br>1 = Max number of repetitions has been reached.<br>A repetition consists of transmitted characters or successive NACK.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_TXBUFE"></a><b>US_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_TXBUFE">AT91C_US_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_RXBUFF"></a><b>US_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_RXBUFF">AT91C_US_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="US_NACK"></a><b>US_NACK</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_NACK">AT91C_US_NACK</a></font></td><td><b>Non Acknowledge</b><br>0 = A Non Acknowledge has not been detected.<br>1 = A Non Acknowledge has been detected.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="US_RIIC"></a><b>US_RIIC</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_RIIC">AT91C_US_RIIC</a></font></td><td><b>Ring INdicator Input Change Flag</b><br>0 = No input change has been detected on the RI pin since the last read of US_CSR.<br>1 = An input change has been detected on the RI pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="US_DSRIC"></a><b>US_DSRIC</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_DSRIC">AT91C_US_DSRIC</a></font></td><td><b>Data Set Ready Input Change Flag</b><br>0 = No input change has been detected on the DSR pin since the last read of US_CSR.<br>1 = An input change has been detected on the DSR pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="US_DCDIC"></a><b>US_DCDIC</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_DCDIC">AT91C_US_DCDIC</a></font></td><td><b>Data Carrier Flag</b><br>0 = No input change has been detected on the DCD pin since the last read of US_CSR.<br>1 = An input change has been detected on the DCD pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="US_CTSIC"></a><b>US_CTSIC</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_CTSIC">AT91C_US_CTSIC</a></font></td><td><b>Clear To Send Input Change Flag</b><br>0 = No input change has been detected on the CTS pin since the last read of US_CSR.<br>1 = An input change has been detected on the CTS pin.</td></tr>
</null></table>
<a name="US_IMR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S64_h.html#AT91_REG">AT91_REG</a></i> US_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S64_h.html#AT91C_US1_IMR">AT91C_US1_IMR</a></i> 0xFFFC4010</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S64_h.html#AT91C_US0_IMR">AT91C_US0_IMR</a></i> 0xFFFC0010</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="US_RXBRK"></a><b>US_RXBRK</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_RXBRK">AT91C_US_RXBRK</a></font></td><td><b>Break Received/End of Break</b><br>0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.<br>1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_TIMEOUT"></a><b>US_TIMEOUT</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_TIMEOUT">AT91C_US_TIMEOUT</a></font></td><td><b>Receiver Time-out</b><br>0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.<br>1 = There has been a time-out since the last Start Time-out command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="US_ITERATION"></a><b>US_ITERATION</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_ITERATION">AT91C_US_ITERATION</a></font></td><td><b>Max number of Repetitions Reached</b><br>Note: This bit will operate only in IS07816 mode, Protocol T = 0.<br>0 = Max number of repetitions has not been reached.<br>1 = Max number of repetitions has been reached.<br>A repetition consists of transmitted characters or successive NACK.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_TXBUFE"></a><b>US_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_TXBUFE">AT91C_US_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_RXBUFF"></a><b>US_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_RXBUFF">AT91C_US_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="US_NACK"></a><b>US_NACK</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_NACK">AT91C_US_NACK</a></font></td><td><b>Non Acknowledge</b><br>0 = A Non Acknowledge has not been detected.<br>1 = A Non Acknowledge has been detected.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="US_RIIC"></a><b>US_RIIC</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_RIIC">AT91C_US_RIIC</a></font></td><td><b>Ring INdicator Input Change Flag</b><br>0 = No input change has been detected on the RI pin since the last read of US_CSR.<br>1 = An input change has been detected on the RI pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="US_DSRIC"></a><b>US_DSRIC</b><font size="-2"><br><a href="AT91SAM7S64_h.html#AT91C_US_DSRIC">AT91C_US_DSRIC</a></font></td><td><b>Data Set Ready Input Change Flag</b><br>0 = No input change has been detected on the DSR pin si