?? at91sam7s64_inc.h
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#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
// *****************************************************************************
// *** Register offset in AT91S_ADC structure ***
#define ADC_CR ( 0) // ADC Control Register
#define ADC_MR ( 4) // ADC Mode Register
#define ADC_CHER (16) // ADC Channel Enable Register
#define ADC_CHDR (20) // ADC Channel Disable Register
#define ADC_CHSR (24) // ADC Channel Status Register
#define ADC_SR (28) // ADC Status Register
#define ADC_LCDR (32) // ADC Last Converted Data Register
#define ADC_IER (36) // ADC Interrupt Enable Register
#define ADC_IDR (40) // ADC Interrupt Disable Register
#define ADC_IMR (44) // ADC Interrupt Mask Register
#define ADC_CDR0 (48) // ADC Channel Data Register 0
#define ADC_CDR1 (52) // ADC Channel Data Register 1
#define ADC_CDR2 (56) // ADC Channel Data Register 2
#define ADC_CDR3 (60) // ADC Channel Data Register 3
#define ADC_CDR4 (64) // ADC Channel Data Register 4
#define ADC_CDR5 (68) // ADC Channel Data Register 5
#define ADC_CDR6 (72) // ADC Channel Data Register 6
#define ADC_CDR7 (76) // ADC Channel Data Register 7
#define ADC_RPR (256) // Receive Pointer Register
#define ADC_RCR (260) // Receive Counter Register
#define ADC_TPR (264) // Transmit Pointer Register
#define ADC_TCR (268) // Transmit Counter Register
#define ADC_RNPR (272) // Receive Next Pointer Register
#define ADC_RNCR (276) // Receive Next Counter Register
#define ADC_TNPR (280) // Transmit Next Pointer Register
#define ADC_TNCR (284) // Transmit Next Counter Register
#define ADC_PTCR (288) // PDC Transfer Control Register
#define ADC_PTSR (292) // PDC Transfer Status Register
// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_SSC structure ***
#define SSC_CR ( 0) // Control Register
#define SSC_CMR ( 4) // Clock Mode Register
#define SSC_RCMR (16) // Receive Clock ModeRegister
#define SSC_RFMR (20) // Receive Frame Mode Register
#define SSC_TCMR (24) // Transmit Clock Mode Register
#define SSC_TFMR (28) // Transmit Frame Mode Register
#define SSC_RHR (32) // Receive Holding Register
#define SSC_THR (36) // Transmit Holding Register
#define SSC_RSHR (48) // Receive Sync Holding Register
#define SSC_TSHR (52) // Transmit Sync Holding Register
#define SSC_SR (64) // Status Register
#define SSC_IER (68) // Interrupt Enable Register
#define SSC_IDR (72) // Interrupt Disable Register
#define SSC_IMR (76) // Interrupt Mask Register
#define SSC_RPR (256) // Receive Pointer Register
#define SSC_RCR (260) // Receive Counter Register
#define SSC_TPR (264) // Transmit Pointer Register
#define SSC_TCR (268) // Transmit Counter Register
#define SSC_RNPR (272) // Receive Next Pointer Register
#define SSC_RNCR (276) // Receive Next Counter Register
#define SSC_TNPR (280) // Transmit Next Pointer Register
#define SSC_TNCR (284) // Transmit Next Counter Register
#define SSC_PTCR (288) // PDC Transfer Control Register
#define SSC_PTSR (292) // PDC Transfer Status Register
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
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