# ----------------------------------------------------------------------------
#          ATMEL Microcontroller Software Support  -  ROUSSET  -
# ----------------------------------------------------------------------------
#  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
#  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
#  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
#  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
#  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
#  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
#  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
#  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
#  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
#  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
# ----------------------------------------------------------------------------
# File Name           : AT91SAM7S64.h
# Object              : AT91SAM7S64 definitions
# Generated           : AT91 SW Application Group  08/30/2005 (15:53:00)
# 
# CVS Reference       : /AT91SAM7S64.pl/1.21/Tue Aug 30 11:55:03 2005//
# CVS Reference       : /SYS_SAM7S.pl/1.2/Tue Feb  1 17:01:52 2005//
# CVS Reference       : /MC_SAM7S.pl/1.3/Fri May 20 14:12:30 2005//
# CVS Reference       : /PMC_SAM7S_USB.pl/1.4/Tue Feb  8 13:58:22 2005//
# CVS Reference       : /RSTC_SAM7S.pl/1.2/Wed Jul 13 14:57:40 2005//
# CVS Reference       : /UDP_SAM7S.pl/1.1/Tue May 10 11:34:52 2005//
# CVS Reference       : /PWM_SAM7S.pl/1.1/Tue May 10 11:53:07 2005//
# CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
# CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
# CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
# CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
# CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
# CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
# CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
# CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
# CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
# CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
# CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
# CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
# CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
# CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
# ----------------------------------------------------------------------------

rdf.version=1

~sysinclude=arm_default.rdf
~sysinclude=arm_status.rdf
# ========== Register definition for SYS peripheral ========== 
# ========== Register definition for AIC peripheral ========== 
AT91C_AIC_IVR.name="AT91C_AIC_IVR"
AT91C_AIC_IVR.description="IRQ Vector Register"
AT91C_AIC_IVR.helpkey="IRQ Vector Register"
AT91C_AIC_IVR.access=memorymapped
AT91C_AIC_IVR.address=0xFFFFF100
AT91C_AIC_IVR.width=32
AT91C_AIC_IVR.byteEndian=little
AT91C_AIC_IVR.permission.write=none
AT91C_AIC_SMR.name="AT91C_AIC_SMR"
AT91C_AIC_SMR.description="Source Mode Register"
AT91C_AIC_SMR.helpkey="Source Mode Register"
AT91C_AIC_SMR.access=memorymapped
AT91C_AIC_SMR.address=0xFFFFF000
AT91C_AIC_SMR.width=32
AT91C_AIC_SMR.byteEndian=little
AT91C_AIC_FVR.name="AT91C_AIC_FVR"
AT91C_AIC_FVR.description="FIQ Vector Register"
AT91C_AIC_FVR.helpkey="FIQ Vector Register"
AT91C_AIC_FVR.access=memorymapped
AT91C_AIC_FVR.address=0xFFFFF104
AT91C_AIC_FVR.width=32
AT91C_AIC_FVR.byteEndian=little
AT91C_AIC_FVR.permission.write=none
AT91C_AIC_DCR.name="AT91C_AIC_DCR"
AT91C_AIC_DCR.description="Debug Control Register (Protect)"
AT91C_AIC_DCR.helpkey="Debug Control Register (Protect)"
AT91C_AIC_DCR.access=memorymapped
AT91C_AIC_DCR.address=0xFFFFF138
AT91C_AIC_DCR.width=32
AT91C_AIC_DCR.byteEndian=little
AT91C_AIC_EOICR.name="AT91C_AIC_EOICR"
AT91C_AIC_EOICR.description="End of Interrupt Command Register"
AT91C_AIC_EOICR.helpkey="End of Interrupt Command Register"
AT91C_AIC_EOICR.access=memorymapped
AT91C_AIC_EOICR.address=0xFFFFF130
AT91C_AIC_EOICR.width=32
AT91C_AIC_EOICR.byteEndian=little
AT91C_AIC_EOICR.type=enum
AT91C_AIC_EOICR.enum.0.name=*** Write only ***
AT91C_AIC_EOICR.enum.1.name=Error
AT91C_AIC_SVR.name="AT91C_AIC_SVR"
AT91C_AIC_SVR.description="Source Vector Register"
AT91C_AIC_SVR.helpkey="Source Vector Register"
AT91C_AIC_SVR.access=memorymapped
AT91C_AIC_SVR.address=0xFFFFF080
AT91C_AIC_SVR.width=32
AT91C_AIC_SVR.byteEndian=little
AT91C_AIC_FFSR.name="AT91C_AIC_FFSR"
AT91C_AIC_FFSR.description="Fast Forcing Status Register"
AT91C_AIC_FFSR.helpkey="Fast Forcing Status Register"
AT91C_AIC_FFSR.access=memorymapped
AT91C_AIC_FFSR.address=0xFFFFF148
AT91C_AIC_FFSR.width=32
AT91C_AIC_FFSR.byteEndian=little
AT91C_AIC_FFSR.permission.write=none
AT91C_AIC_ICCR.name="AT91C_AIC_ICCR"
AT91C_AIC_ICCR.description="Interrupt Clear Command Register"
AT91C_AIC_ICCR.helpkey="Interrupt Clear Command Register"
AT91C_AIC_ICCR.access=memorymapped
AT91C_AIC_ICCR.address=0xFFFFF128
AT91C_AIC_ICCR.width=32
AT91C_AIC_ICCR.byteEndian=little
AT91C_AIC_ICCR.type=enum
AT91C_AIC_ICCR.enum.0.name=*** Write only ***
AT91C_AIC_ICCR.enum.1.name=Error
AT91C_AIC_ISR.name="AT91C_AIC_ISR"
AT91C_AIC_ISR.description="Interrupt Status Register"
AT91C_AIC_ISR.helpkey="Interrupt Status Register"
AT91C_AIC_ISR.access=memorymapped
AT91C_AIC_ISR.address=0xFFFFF108
AT91C_AIC_ISR.width=32
AT91C_AIC_ISR.byteEndian=little
AT91C_AIC_ISR.permission.write=none
AT91C_AIC_IMR.name="AT91C_AIC_IMR"
AT91C_AIC_IMR.description="Interrupt Mask Register"
AT91C_AIC_IMR.helpkey="Interrupt Mask Register"
AT91C_AIC_IMR.access=memorymapped
AT91C_AIC_IMR.address=0xFFFFF110
AT91C_AIC_IMR.width=32
AT91C_AIC_IMR.byteEndian=little
AT91C_AIC_IMR.permission.write=none
AT91C_AIC_IPR.name="AT91C_AIC_IPR"
AT91C_AIC_IPR.description="Interrupt Pending Register"
AT91C_AIC_IPR.helpkey="Interrupt Pending Register"
AT91C_AIC_IPR.access=memorymapped
AT91C_AIC_IPR.address=0xFFFFF10C
AT91C_AIC_IPR.width=32
AT91C_AIC_IPR.byteEndian=little
AT91C_AIC_IPR.permission.write=none
AT91C_AIC_FFER.name="AT91C_AIC_FFER"
AT91C_AIC_FFER.description="Fast Forcing Enable Register"
AT91C_AIC_FFER.helpkey="Fast Forcing Enable Register"
AT91C_AIC_FFER.access=memorymapped
AT91C_AIC_FFER.address=0xFFFFF140
AT91C_AIC_FFER.width=32
AT91C_AIC_FFER.byteEndian=little
AT91C_AIC_FFER.type=enum
AT91C_AIC_FFER.enum.0.name=*** Write only ***
AT91C_AIC_FFER.enum.1.name=Error
AT91C_AIC_IECR.name="AT91C_AIC_IECR"
AT91C_AIC_IECR.description="Interrupt Enable Command Register"
AT91C_AIC_IECR.helpkey="Interrupt Enable Command Register"
AT91C_AIC_IECR.access=memorymapped
AT91C_AIC_IECR.address=0xFFFFF120
AT91C_AIC_IECR.width=32
AT91C_AIC_IECR.byteEndian=little
AT91C_AIC_IECR.type=enum
AT91C_AIC_IECR.enum.0.name=*** Write only ***
AT91C_AIC_IECR.enum.1.name=Error
AT91C_AIC_ISCR.name="AT91C_AIC_ISCR"
AT91C_AIC_ISCR.description="Interrupt Set Command Register"
AT91C_AIC_ISCR.helpkey="Interrupt Set Command Register"
AT91C_AIC_ISCR.access=memorymapped
AT91C_AIC_ISCR.address=0xFFFFF12C
AT91C_AIC_ISCR.width=32
AT91C_AIC_ISCR.byteEndian=little
AT91C_AIC_ISCR.type=enum
AT91C_AIC_ISCR.enum.0.name=*** Write only ***
AT91C_AIC_ISCR.enum.1.name=Error
AT91C_AIC_FFDR.name="AT91C_AIC_FFDR"
AT91C_AIC_FFDR.description="Fast Forcing Disable Register"
AT91C_AIC_FFDR.helpkey="Fast Forcing Disable Register"
AT91C_AIC_FFDR.access=memorymapped
AT91C_AIC_FFDR.address=0xFFFFF144
AT91C_AIC_FFDR.width=32
AT91C_AIC_FFDR.byteEndian=little
AT91C_AIC_FFDR.type=enum
AT91C_AIC_FFDR.enum.0.name=*** Write only ***
AT91C_AIC_FFDR.enum.1.name=Error
AT91C_AIC_CISR.name="AT91C_AIC_CISR"
AT91C_AIC_CISR.description="Core Interrupt Status Register"
AT91C_AIC_CISR.helpkey="Core Interrupt Status Register"
AT91C_AIC_CISR.access=memorymapped
AT91C_AIC_CISR.address=0xFFFFF114
AT91C_AIC_CISR.width=32
AT91C_AIC_CISR.byteEndian=little
AT91C_AIC_CISR.permission.write=none
AT91C_AIC_IDCR.name="AT91C_AIC_IDCR"
AT91C_AIC_IDCR.description="Interrupt Disable Command Register"
AT91C_AIC_IDCR.helpkey="Interrupt Disable Command Register"
AT91C_AIC_IDCR.access=memorymapped
AT91C_AIC_IDCR.address=0xFFFFF124
AT91C_AIC_IDCR.width=32
AT91C_AIC_IDCR.byteEndian=little
AT91C_AIC_IDCR.type=enum
AT91C_AIC_IDCR.enum.0.name=*** Write only ***
AT91C_AIC_IDCR.enum.1.name=Error
AT91C_AIC_SPU.name="AT91C_AIC_SPU"
AT91C_AIC_SPU.description="Spurious Vector Register"
AT91C_AIC_SPU.helpkey="Spurious Vector Register"
AT91C_AIC_SPU.access=memorymapped
AT91C_AIC_SPU.address=0xFFFFF134
AT91C_AIC_SPU.width=32
AT91C_AIC_SPU.byteEndian=little
# ========== Register definition for PDC_DBGU peripheral ========== 
AT91C_DBGU_TCR.name="AT91C_DBGU_TCR"
AT91C_DBGU_TCR.description="Transmit Counter Register"
AT91C_DBGU_TCR.helpkey="Transmit Counter Register"
AT91C_DBGU_TCR.access=memorymapped
AT91C_DBGU_TCR.address=0xFFFFF30C
AT91C_DBGU_TCR.width=32
AT91C_DBGU_TCR.byteEndian=little
AT91C_DBGU_RNPR.name="AT91C_DBGU_RNPR"
AT91C_DBGU_RNPR.description="Receive Next Pointer Register"
AT91C_DBGU_RNPR.helpkey="Receive Next Pointer Register"
AT91C_DBGU_RNPR.access=memorymapped
AT91C_DBGU_RNPR.address=0xFFFFF310
AT91C_DBGU_RNPR.width=32
AT91C_DBGU_RNPR.byteEndian=little
AT91C_DBGU_TNPR.name="AT91C_DBGU_TNPR"
AT91C_DBGU_TNPR.description="Transmit Next Pointer Register"
AT91C_DBGU_TNPR.helpkey="Transmit Next Pointer Register"
AT91C_DBGU_TNPR.access=memorymapped
AT91C_DBGU_TNPR.address=0xFFFFF318
AT91C_DBGU_TNPR.width=32
AT91C_DBGU_TNPR.byteEndian=little
AT91C_DBGU_TPR.name="AT91C_DBGU_TPR"
AT91C_DBGU_TPR.description="Transmit Pointer Register"
AT91C_DBGU_TPR.helpkey="Transmit Pointer Register"
AT91C_DBGU_TPR.access=memorymapped
AT91C_DBGU_TPR.address=0xFFFFF308
AT91C_DBGU_TPR.width=32
AT91C_DBGU_TPR.byteEndian=little
AT91C_DBGU_RPR.name="AT91C_DBGU_RPR"
AT91C_DBGU_RPR.description="Receive Pointer Register"
AT91C_DBGU_RPR.helpkey="Receive Pointer Register"
AT91C_DBGU_RPR.access=memorymapped
AT91C_DBGU_RPR.address=0xFFFFF300
AT91C_DBGU_RPR.width=32
AT91C_DBGU_RPR.byteEndian=little
AT91C_DBGU_RCR.name="AT91C_DBGU_RCR"
AT91C_DBGU_RCR.description="Receive Counter Register"
AT91C_DBGU_RCR.helpkey="Receive Counter Register"
AT91C_DBGU_RCR.access=memorymapped
AT91C_DBGU_RCR.address=0xFFFFF304
AT91C_DBGU_RCR.width=32
AT91C_DBGU_RCR.byteEndian=little
AT91C_DBGU_RNCR.name="AT91C_DBGU_RNCR"
AT91C_DBGU_RNCR.description="Receive Next Counter Register"
AT91C_DBGU_RNCR.helpkey="Receive Next Counter Register"
AT91C_DBGU_RNCR.access=memorymapped
AT91C_DBGU_RNCR.address=0xFFFFF314
AT91C_DBGU_RNCR.width=32
AT91C_DBGU_RNCR.byteEndian=little
AT91C_DBGU_PTCR.name="AT91C_DBGU_PTCR"
AT91C_DBGU_PTCR.description="PDC Transfer Control Register"
AT91C_DBGU_PTCR.helpkey="PDC Transfer Control Register"
AT91C_DBGU_PTCR.access=memorymapped
AT91C_DBGU_PTCR.address=0xFFFFF320
AT91C_DBGU_PTCR.width=32
AT91C_DBGU_PTCR.byteEndian=little
AT91C_DBGU_PTCR.type=enum
AT91C_DBGU_PTCR.enum.0.name=*** Write only ***
AT91C_DBGU_PTCR.enum.1.name=Error
AT91C_DBGU_PTSR.name="AT91C_DBGU_PTSR"
AT91C_DBGU_PTSR.description="PDC Transfer Status Register"
AT91C_DBGU_PTSR.helpkey="PDC Transfer Status Register"
AT91C_DBGU_PTSR.access=memorymapped
AT91C_DBGU_PTSR.address=0xFFFFF324
AT91C_DBGU_PTSR.width=32
AT91C_DBGU_PTSR.byteEndian=little
AT91C_DBGU_PTSR.permission.write=none
AT91C_DBGU_TNCR.name="AT91C_DBGU_TNCR"
AT91C_DBGU_TNCR.description="Transmit Next Counter Register"
AT91C_DBGU_TNCR.helpkey="Transmit Next Counter Register"
AT91C_DBGU_TNCR.access=memorymapped
AT91C_DBGU_TNCR.address=0xFFFFF31C
AT91C_DBGU_TNCR.width=32
AT91C_DBGU_TNCR.byteEndian=little
# ========== Register definition for DBGU peripheral ========== 
AT91C_DBGU_EXID.name="AT91C_DBGU_EXID"
AT91C_DBGU_EXID.description="Chip ID Extension Register"
AT91C_DBGU_EXID.helpkey="Chip ID Extension Register"
AT91C_DBGU_EXID.access=memorymapped
AT91C_DBGU_EXID.address=0xFFFFF244
AT91C_DBGU_EXID.width=32
AT91C_DBGU_EXID.byteEndian=little
AT91C_DBGU_EXID.permission.write=none
AT91C_DBGU_BRGR.name="AT91C_DBGU_BRGR"
AT91C_DBGU_BRGR.description="Baud Rate Generator Register"
AT91C_DBGU_BRGR.helpkey="Baud Rate Generator Register"
AT91C_DBGU_BRGR.access=memorymapped
AT91C_DBGU_BRGR.address=0xFFFFF220
AT91C_DBGU_BRGR.width=32
AT91C_DBGU_BRGR.byteEndian=little
AT91C_DBGU_IDR.name="AT91C_DBGU_IDR"
AT91C_DBGU_IDR.description="Interrupt Disable Register"
AT91C_DBGU_IDR.helpkey="Interrupt Disable Register"
AT91C_DBGU_IDR.access=memorymapped
AT91C_DBGU_IDR.address=0xFFFFF20C
AT91C_DBGU_IDR.width=32
AT91C_DBGU_IDR.byteEndian=little
AT91C_DBGU_IDR.type=enum
AT91C_DBGU_IDR.enum.0.name=*** Write only ***
AT91C_DBGU_IDR.enum.1.name=Error
AT91C_DBGU_CSR.name="AT91C_DBGU_CSR"
AT91C_DBGU_CSR.description="Channel Status Register"
AT91C_DBGU_CSR.helpkey="Channel Status Register"
AT91C_DBGU_CSR.access=memorymapped
AT91C_DBGU_CSR.address=0xFFFFF214
AT91C_DBGU_CSR.width=32
AT91C_DBGU_CSR.byteEndian=little
AT91C_DBGU_CSR.permission.write=none
AT91C_DBGU_CIDR.name="AT91C_DBGU_CIDR"
AT91C_DBGU_CIDR.description="Chip ID Register"
AT91C_DBGU_CIDR.helpkey="Chip ID Register"
AT91C_DBGU_CIDR.access=memorymapped
AT91C_DBGU_CIDR.address=0xFFFFF240
AT91C_DBGU_CIDR.width=32
AT91C_DBGU_CIDR.byteEndian=little
AT91C_DBGU_CIDR.permission.write=none
AT91C_DBGU_MR.name="AT91C_DBGU_MR"
AT91C_DBGU_MR.description="Mode Register"
AT91C_DBGU_MR.helpkey="Mode Register"
AT91C_DBGU_MR.access=memorymapped
AT91C_DBGU_MR.address=0xFFFFF204
AT91C_DBGU_MR.width=32
AT91C_DBGU_MR.byteEndian=little
AT91C_DBGU_IMR.name="AT91C_DBGU_IMR"
AT91C_DBGU_IMR.description="Interrupt Mask Register"
AT91C_DBGU_IMR.helpkey="Interrupt Mask Register"
AT91C_DBGU_IMR.access=memorymapped