;              received.  Because the SPIBUF register was not read after
;              the first interrupt, the second character should generate 
;              a receiver overrun interrupt.  This is checked in the low
;              priority ISR by reading the RECEIVER OVERRUN Flag Bit in
;              the SPI Status Register (SPISTS).  The word "BAD" will be 
;              in B2 at the end of the test is an error condition is
;              detected.
; Originator: J. Crankshaw
;
; Calling Convention: Assumes DP = 224 (7000h - 707fh)
;
;   Variables		on Entry		on Exit
; ----------------------------------------------------------------
; ----------------------------------------------------------------
; History: 
; Last Update:	10-18-96
;===========================================================================
SPILOOP:
* Initialize Auxilliary Registers
	LAR	AR2,#RX1_ERLOG
	LAR	AR3,#RX_char1
	LAR	AR4,#INT_FLAG
	LAR	AR5,#Ivr1
	MAR	*,AR2		; use AR2 as the next Aux register

* initialize SPI in master mode
	SPLK	#0087h,SPICCR	; Reset SPI by writing 1 to SWRST
	SPLK	#000Ch,SPICTL	; Disable ints & TALK, normal clock, master mode
	SPLK	#0000h,SPIPRI	; Set SPI interrupt to level 1 (high priority)
	SPLK	#0000h,SPIBRR	; Set baud rate to 'fastest'
	SPLK	#000Fh,SPICTL	; Enable TALK & RCV int, CLK ph 1, master mode
	SPLK	#0052h,SPIPC1	; STE pin drives 1, SPICLK to clock out
	SPLK	#0022h,SPIPC2	; Set SIMO & SOMI functions to serial I/O
	SPLK	#0007h,SPICCR	; Release SWRST, clock polarity 0, 8 bits

* Initialize DSP for interrupts
     LAR  AR6,#IMR       ; 
     LAR  AR7,#IFR       ;
     MAR  *,AR6
     LACL #011h          ;
	SACL *,AR7          ; Enable interrupts 1 & 5 only
	LACL	*    		; Clear IFR by reading and
	SACL	*,AR2		; writing contents back into itself

	CLRC	INTM           ; Enable DSP interrupts

**********************************************************
* Begin 1st Xmit (to SPI #1)                             *
**********************************************************
	LACC	#Char1		; ACC <= 1st byte to xmit
	SACL	SPIDAT		; Xmit 1st byte
	IDLE			     ; Wait for rcv interrupt, returns w/ ARP=AR2

**********************************************************
* Setup for transmit to SPI #2 with interrupt level 2	 *
**********************************************************
	SPLK	#0040h,SPIPRI	; Set SPI interrupt to level 2 (low priority)
	LAR	AR2,#RX2_ERLOG ; storage for 2nd RX error log
	LAR	AR3,#RX_char2  ; storage for 2nd char
	LAR	AR4,#OVER_RUN  ; storage for 2nd SPISTS
	LAR	AR5,#Ivr2	     ; Storage for level 2 IVR

* Read-modify-write sequence to enable Receiver OVERRUN interrupt
     LACL SPICTL         ; read:   ACC <= SPI control register
     OR   #010h          ; modify: set bit 4, Receiver OVERRUN interrupt enable bit
     SACL SPICTL         ; write:  SPICTL <= ACC

**********************************************************
* Begin 2nd Xmit (to SPI #2)                             *
**********************************************************
	LACC	#Char2		; ACC <= 2nd byte to xmit
	SACL	SPIDAT		; Xmit 2nd byte
	IDLE			     ; Wait for rcv interrupt, returns w/ ARP=AR2

     RET
*******************************************************************************
*                ISR's                                                        *
*******************************************************************************
;==============================================================================
; I S R  -  PHANTOM
;
; Description:	ISR used to trap spurious interrupts.
;              Reads System Interrupt Vector register to capture
;              vector of module that caused the interrupt.
;
; Modifies:	Changes DP and ACC.  Loads vector into 61h and BADh into 60h.
;
; Last Update:	10-17-96
;==============================================================================
PHANTOM 	
     LDP  #DP_PF1        ; go to peripheral file data page 1
	LACL	SYSIVR		; ACC <= [SYSIVR]           
     LDP  #0             ; go to first data page, with B2
	SACL	B2_SADDR+1	; 61h <= [SYSIVR]
	SPLK	#0deadh,B2_SADDR	; 60h <= "dead" value indicates error
	B	END		; Terminate gracefully

;==============================================================================
; I S R  -  INT1 interrupt service routine
;
; Description:	ISR for SPI Rx/Tx Interrupt.  Assumes no other sources are
;			enabled on INT1 besides the SPI.  No context save/restore
;			is performed since this is test code only.  No other modules
;			are running.
;
; Modifies:	ARP, ACC, assumes AR2-AR5 loaded in SPILOOP subroutine
;
; Last Update:	2 Feb 98
;==============================================================================
INT1_ISR  			; Interrupt 1 Interrupt Service Routine

	MAR	*,AR3          ; use RX_char1 for next indirect
     LACL SPIEMU         ; ACC <= SPI Emualtion Buffer Register (mirror of SPIBUF)
     SACL *,AR4          ; store value in B2 @ RX_char1
                         ; use INT_FLAG for next indirect
	LACL	SPISTS		; ACC <= SPI Status Register
     AND  #0C0h          ; clear all bits except SPI INT FLAG bit (SPISTS.6)
                         ; and RECEIVER OVERRUN bit (SPISTS.7)
     SACL *,AR2          ; store SPISTS value to INT_FLAG
                         ; use ERRLOG for next indirect
     AND  #040h          ; clear all bits except SPI INT FLAG bit (SPISTS.6)
     XOR  #040h          ; xor will clear bit 6 in ACC if SPISTS.6 was set
     BCND IVR,EQ         ; branch to next section if bit 6 was set
     SPLK #0BADh,*,AR5   ; Write "BAD" to ERRLOG 
                         ; use IVR1 for next indirect
IVR	MAR  *,AR5          ; use IVR1 for next indirect
     LACL	SYSIVR		; ACC <= interrupt vector
	SACL	*,0,AR2		; Ivr[i] <= interrupt vector
				     ; Use ERRLOG for next indirect
     XOR  #SPIvector     ; compare with expected value
     BCND RMW1,EQ        ; skip error writing if match
     SPLK #0BADh,*       ; write BAD to error log in B2

* Read-modify-write sequence to disable SPI interrupts
RMW1 LACL SPICTL         ; read:   ACC <= SPI control register
     AND  #0FEh          ; modify: clear bit 0, SPI interrupt enable bit
     SACL SPICTL         ; write:  SPICTL <= ACC

	CLRC	INTM		     ; Enable DSP interrupts
	RET			     ; Return from interrupt

;==============================================================================
; I S R  -  INT5 interrupt service routine
;
; Description:	ISR for SPI Rx/Tx Interrupt.  Assumes no other sources are
;			enabled on INT5 besides the SPI.  No context save/restore
;			is performed since this is test code only.  No other modules
;			are running.
;
; Modifies:	ARP, ACC, assumes AR2-AR5 loaded in SPILOOP subroutine
;
; Last Update:	2 Feb 98
;==============================================================================
INT5_ISR  			; Interrupt 5 Interrupt Service Routine

	MAR	*,AR3          ; use RX_char2 for next indirect
     LACL SPIBUF         ; ACC <= SPI Buffer Register
     SACL *,AR4          ; store value in B2 @ RX_char2
                         ; use OVER_RUN for next indirect
	LACL	SPISTS		; ACC <= SPI Status Register
     AND  #0C0h          ; clear all bits except SPI INT FLAG bit (SPISTS.6)
                         ; and RECEIVER OVERRUN bit (SPISTS.7)
     SACL *,AR2          ; store SPISTS value to OVER_RUN
                         ; use ERRLOG for next indirect
     AND  #080h          ; clear all bits except RECEIVER OVERRUN bit (SPISTS.7)
     XOR  #080h          ; xor will clear bit 7 in ACC if SPISTS.7 was set
     BCND IVR2,EQ        ; branch to next section if bit 7 was set
     SPLK #0BADh,*,AR5   ; Write "BAD" to ERRLOG 
                         ; use IVR1 for next indirect
IVR2	MAR  *,AR5
     LACL	SYSIVR		; ACC <= interrupt vector
	SACL	*,0,AR2		; Ivr[i] <= interrupt vector
				     ; Use ERRLOG for next indirect
     XOR  #SPIvector       ; compare with expected value
     BCND RMW2,EQ        ; skip error writing if match
     SPLK #0BADh,*       ; write BAD to error log in B2

* Read-modify-write sequence to disable SPI interrupts
RMW2 LACL SPICTL         ; read:   ACC <= SPI control register
     AND  #0EEh          ; modify: clear bits 0 & 4, SPI interrupt enable 
                         ;         and receiver overrun bits
     SACL SPICTL         ; write:  SPICTL <= ACC

	CLRC	INTM		     ; Enable DSP interrupts
	RET			     ; Return from interrupt

	.end