/*-------------------------------------------------------------------------*/
/*  LINKER COMMAND FILE - MEMORY SPECIFICATION for F240 EVM  	    	   */
/*  Last update 31 DEC 96								   */
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MEMORY
{
    PAGE 0 :   	VECS	: origin =    0h , length =   040h	 /* PROGRAM */
			PVECS: origin =   40h , length =    70h  /* Peripheral Interrupt Vectors */
	       	PROG	: origin =  0b0h , length =  3F50h	 /* FLASH or external */
			XPM	: origin = 4000h , length =  1000h	 /* XPM     */
			ISR	: origin = 5000h , length =  1000h	 /* ISR    */
			B0PGM : origin = 0fe00h , length =  0100h	 /* B0    */

    PAGE 1 :   	MMRS	: origin =    0h , length =   05Fh	 /* MMRS    */
	       	B2	: origin = 0060h , length =   020h	 /* DARAM   */
	       	B0	: origin = 0200h , length =  0100h	 /* DARAM   */
	       	B1	: origin = 0300h , length =  0100h	 /* DARAM   */
	       	DATA	: origin = 8000h , length =  8000h	 /* XDM     */
}

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/* SECTIONS ALLOCATION                                                     */
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SECTIONS
{
    .reset   : { } > VECS      PAGE 0 	   /* Interrupt Vector Table     */
    .vectors : { } > VECS      PAGE 0	   /* INTERRUPT VECTOR TABLE	   */
    .pvecs   : { } > PVECS     PAGE 0	   /* Peripheral INTERRUPT VECTOR TABLE	   */
    .start   : { } > PROG      PAGE 0        /* CODE                       */
    .text    : { } > PROG      PAGE 0	   /* CODE			  	   */
    .b0pgm   : { } > B0PGM     PAGE 0	   /* CODE			  	   */
    .data    : { } > PROG      PAGE 0	   /* INITIALIZATION DATA TABLES */
    .xmem    : { } > XPM       PAGE 0	   /* External Program Memory	   */
    .xint    : { } > ISR       PAGE 0	   /* External Interrupt Routine */
    .mmrs    : { } > MMRS      PAGE 1	   /* Memory Mapped Registers	   */
    .blk0    : { } > B0        PAGE 1	   /* Block B0 - page 4 	   */
    .bss     : { } > B2        PAGE 1	   /* Block B2 - page 0 	   */
    .blk1    : { } > B1        PAGE 1	   /* Block B1 - page ? 	   */
    .blk3    : { } > DATA      PAGE 1	   /* External Data Memory	   */
}