?? twicreg.h
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#define CSC_CbGCOEF 0x64
// define CSC Green coef of Cr (R/W)
// [7:0] 0.8-bit fixed point (frac * 2^8)
#define CSC_CrGCOEF_REG 0x9A
#define CSC_CrGCOEF_DEFAULT 0xD0 //=0.813
#define CSC_CrGCOEF 0xD0
// define CSC Blue coef of Cb (R/W)
// [7:0] 2.6-bit fixed point (int *2^6 + frac*2^6)
#define CSC_CbBCOEF_REG 0x9B
#define CSC_CbBCOEF_DEFAULT 0x81 //=2.016
#define CSC_CbBCOEF 0x81
// Pattern color gradient & dithering mode register, 0x9C
// [7:4] when P0_09[7:6] set to 11. this bit may set color gradient at pattern 2,3,4,5
// [3:2] reserved
// [1:0] dithering mode. enabled by P0_09[0]
// 00: 4-bit output
// 01: 5-bit output
// 10: 6-bit output
// 11: 7-bit output
#define PATTERN_GRA_DITH_REG 0x9C
#define PATTERN_GRA_DITH_DEFAULT 0x00
#define PATTERN_GRA_DITH 0x02
// output timing control
// Display window horizontal/vertical start LSB/MSB register, 0xB0~0xB3
// [7:0] LSB
// [7:4] reserved
// [3:0] MSB
// when PAUTO_SYNC is enabled, DWVS is set by auto-detection (default ?)
//
// Display window horizontal/vertical width(size) LSB/MSB register, 0xB4~0xB7
// [7:0] LSB
// [7:4] reserved
// [3:0] MSB
//
// Display panel horizontal/vertical total dots per scan line LSB/MSB register,0xB8~0xBB
// [7:0] LSB
// [7:4] reserved
// [3:0] MSB
//
// Display panel Hsync/Vsync width LSB/MSB register, 0xBC~0xBF
// [7:0] LSB
// [7:4] reserved
// [3:0] MSB
//
#define DWHS_L_REG 0xB0
#define DWHS_H_REG 0xB1
#define DWVS_L_REG 0xB2
#define DWVS_H_REG 0xB3
#define DWHSZ_L_REG 0xB4
#define DWHSZ_H_REG 0xB5
#define DWVSZ_L_REG 0xB6
#define DWVSZ_H_REG 0xB7
#define PH_TOT_L_REG 0xB8
#define PH_TOT_H_REG 0xB9
#define PV_TOT_L_REG 0xBA
#define PV_TOT_H_REG 0xBB
#define PH_PW_L_REG 0xBC
#define PH_PW_H_REG 0xBD
#define PV_PW_L_REG 0xBE
#define PV_PW_H_REG 0xBF
#define DWHS_L 0x20
#define DWHS_H 0x00
#define DWVS_L 0x0D
#define DWVS_H 0x00
#define DWHSZ_L (H_Size&0xFF)
#define DWHSZ_H (H_Size>>8)
#define DWVSZ_L (V_Size&0xFF)
#define DWVSZ_H (V_Size>>8)
#define PH_TOT_L 0x88
#define PH_TOT_H 0x02
#define PV_TOT_L 0x04
#define PV_TOT_H 0x01
#define PH_PW_L 0x10
#define PH_PW_H 0x00
#define PV_PW_L 0x03
#define PV_PW_H 0x00
#define USE_PRESET_OPTIMING 1
// Panel output signal control 3 register, 0xC1
// [7:4] reserved (?)
// [3] DCLK polarity. 0: Normal(default), 1: inverted
// [2] ODCK internal delay(LVDS mode). 0: National standard(default)
// 1: Korean/Non-standard
// [1:0] reserved
#define POUT_CTRL3_REG 0xC1
#define POUT_CTRL3_DEFAULT 0x01
#define POUT_CTRL3 0xC8
// Panel Vsync frame delay control register, 0xC2
// [7] convert interlaced input timing for output timing generation
// [6:5] reserved
// [4] 1: block input Vsync triggering on output Vsync
// 0: allow input Vsync to trigger output Vsync
// [3] 0: short line, i.e., last Hsync is less than 1.0 line
// 1: long line, i.e., last Hsync is greater than 1.0 line
// [2] Save recovery mode
// [1] ignore the input Vsync. this can be used for output free run when input Vsync is not available
// [0] reserved
#define POUT_VSYNC_CTRL_REG 0xC2
#define POUT_VSYNC_CTRL_DEFAULT 0x00
#define POUT_VSYNC_CTRL 0x12
// Output PLL divider 1 register, 0xC8
// [7] reserved
// [6:0] PLL feedback divider. default=124(0x7C)
//
// Output PLL divider 2 register, 0xC9
// [7:5] reserved
// [4:0] PLL input divider. default=27(0x1B)
//
// Output PLL divider 3 register, 0xCA
// [7:6] PLL MUX function select 00: PLLCLK
// 01: Bypass PLL
// 10: Keep High
// 11: Keep high
// [5] ?
// [4] ?
// [3:2] reserved
// [1:0] PLL output divider. default=1
#define PLLDIV_FB_REG 0xC8
#define PLLDIV_FB_DEFAULT 0x7C
#define PLLDIV_IP_REG 0xC9
#define PLLDIV_IP_DEFAULT 0x1B
#define PLLDIV_OP_REG 0xCA
#define PLLDIV_OP_DEFAULT 0x01
#define PLLDIV_FB DFDIV_40
#define PLLDIV_IP DIDIV
#define PLLDIV_OP DODIV
// Horizontal/Vertical main display start, 0xD8~0xDB
// [7:0] LSB
// [7:4] reserved
// [3:0] MSB
#define HMDISP_STR_L_REG 0xD8
#define HMDISP_STR_L_DEFAULT 0x00
#define HMDISP_STR_H_REG 0xD9
#define HMDISP_STR_H_DEFAULT 0x00
#define VMDISP_STR_L_REG 0xDA
#define VMDISP_STR_L_DEFAULT 0x00
#define VMDISP_STR_H_REG 0xDB
#define VMDISP_STR_H_DEFAULT 0x00
#define HMDISP_STR_L 0x00
#define HMDISP_STR_H 0x00
#define VMDISP_STR_L 0x00
#define VMDISP_STR_H 0x00
// Horizontal/Vertical main display size, 0xDC~0xDF
// [7:0] LSB
// [7:4] reserved
// [3:0] MSB
#define HMDISP_SIZE_L_REG 0xDC
#define HMDISP_SIZE_L_DEFAULT 0x00
#define HMDISP_SIZE_H_REG 0xDD
#define HMDISP_SIZE_H_DEFAULT 0x05
#define VMDISP_SIZE_L_REG 0xDE
#define VMDISP_SIZE_L_DEFAULT 0x00
#define VMDISP_SIZE_H_REG 0xDF
#define VMDISP_SIZE_H_DEFAULT 0x04
#define HMDISP_SIZE_L (H_Size&0xFF)
#define HMDISP_SIZE_H (H_Size>>8)
#define VMDISP_SIZE_L (V_Size&0xFF)
#define VMDISP_SIZE_H (V_Size>>8)
// define power management control register (R/W), 0xE0
// [7] when 0, power down whole chip/pull down pads (default = 1)
// [6] power down mode 0: Whole chip power down
// 1: Output pads pull down
// [5] power down ADC, low active
// [4] power down comb video decoder, for internal software test, low active
// [3] power down DisplayPLL
// [2] power down MPLL
// [1] reserved
// [0] power down TC interface, low active
//
// Output pin configuration, 0xE1
// [7:6] Row STV select 00: output both
// 01: output both
// 10: output STV1
// 11: output STV2
// [5:4] Col STH select 00: output both
// 01: output both
// 10: output STH1
// 11: output STH2
// [3] up-down selection
// [2] left-right selection
// [1:0] reserved
#define PW_MGRCTRL_REG 0xE0
#define PW_MGRCTRL_DEFAULT 0x1C
#define OPIN_CFG_REG 0xE1
#define OPIN_CFG_DEFAULT 0x00
#ifdef TCON
#define PW_MGRCTRL 0x9D
#define OPIN_CFG 0xF4
#else
#define PW_MGRCTRL 0x9C
#define OPIN_CFG 0x00
#endif
// GPIO Output Control Register 0xEC
// [7] Set to 1 for power down SAR1 block
// [6] Set to 1 enabling de-bounce process on SRA1 sampled value
// [5:4] XCLK
// [3:0] Reflect SAR1 sampled value
#define GPIO_OUT_CTRL_REG 0xEC
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Page 1 registers definition
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//Infra-Red Register Set
//IR Sampling Tick LSB Register 0x40
#define IR_TickL 0x40
//IR Sampling Tick MSB Register 0x41
#define IR_TickM 0x41
//IR Stream 1~4 Register (when IR_Counter_Mode=0) 0x42~0x45
//IR Duration 1~3 Register (when IR_Counter_Mode=1) 0x42~0x44
#define IR_STREAM1 0x42
#define IR_STREAM2 0x43
#define IR_STREAM3 0x44
#define IR_STREAM4 0x45
//IR Stream 1 Register 0x47
#define IR_STREAM_REG 0x47
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Page 2 registers definition
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Video source selection of Comb filter, 0x00
// [7] reserved
// [6:5] select the number of pixel per scan line
// 00: 858pixels, NTSC, PAL(M)
// 01: 864pixels, PAL(B,D,G,H,I,N,CN), SECAM
// 10: 780pixels, NTSC square pixel, PAL(M) square pixel
// 11: 944pixels, PAL(B,D,G,H,I,N) square pixel
// [4] select the number of scan lines per frame
// 0: 525 (default)
// 1: 625
// [3:1] select SDTV video mode
// 000: NTSC (default)
// 001: PAL(I,B,G,H,D,N)
// 010: PAL(M)
// 011: PAL(CN)
// 100: SECAM
// [0] select input video format
// 0: CVBS composite (default)
// 1: S-Video (separated Y/C)
#define SRCSEL_COMBF_REG 0x00
#define SRCSEL_COMBF_DEFAULT 0x00
#define SRCSEL_COMBF 0x00
// Bandwidth control, 0x01
// [7] invert the select signal for the analog input multiplexer during component video mode
// 0: not inverted(default)
// 1: inverted
// [6] 0: S-video or CVBS
// 1: YPbPr component video input
// [5:4] select luma notch width
// 00: none (default)
// 01: narrow
// 10: medium
// 11: wide
// [3:2] set the chroma low pass filter to wide or narrow
// 00: narrow (default)
// 01: wide
// 10: extra wide
// 11: extra wide
// [1] select the burst gate width
// 0: 5 subcarrier clock cycles (default)
// 1: 10 subcarrier clock cycles
// [0] enable black level correction for 10 blank-to-blank pedestal
// 0: no pedestal subtraction
// 1: pedestal subtraction (default)
#define BW_CTRL_REG 0x01
#define BW_CTRL_DEFAULT 0x01
#define BW_CTRL 0x01
#define ENYPbPr 0x40
// Y/C AGC enable, 0x02
// [7] 0: (default)gain is updated once per line, after DC clamping
// 1: gain is only updated once per field, at the start of vertical blank
// [6] 1: (default) automatically reduce the gain (set in P2_04) by 25%
// when macro-vision encoded signals are detected
// 0: off
// [5:4] analog front end DC clamping
// 00: auto (default)
// 01: backporch only
// 10: synctip only
// 11: off
// [3] 1: (default) enable the digital AGC, used in series with the analog gain
// [2] reserved
// [1] 1: (default) enable the chroma AGC
// 0: the AGC target is used to drive directly the AGC gain
// [0] 1: (default) enable the luma/composite AGC
// 0: use AGC target (P2_04h) to drive directly the AGC gain
#define YC_AGC_REG 0x02
#define YC_AGC_DEFAULT 0x4F
#define YC_AGC 0x4B //not equal to 0x4B, despite of [2] is reserved (?)
// Comb filtering mode, 0x03
// [7:4] reserved
// [3] enable the notch-filter at the luma path after the comb filter.
// This filter can be turned on or off irrespective of the adaptive mode setting
// 0: disable (default), 1: enable
// [2:0] select the filter modes for the composite signal's luma(Y) and chroma (C)
// separation before color demodulation
// 000: (default) fully adaptive comb (2-D adaptive comb)
// 001: vertical adaptive comb (1-D adaptive comb, vertical bomb only)
// 010: 5-tap adaptive comb filter (PAL mode only)
// 011: basic luma notch filter mode (for very noisy and unstable pictures)
// 100: simple 2-tap comb
// 101: simple 3-tap comb
// 110: 5-tap hybrid adaptive comb filter (PAL mode only)
#define COMB_FILTERMODE_REG 0x03
#define COMB_FILTERMODE_DEFAULT 0x00
#define COMB_FILTERMODE 0x00
// Luma AGC target value, 0x04
//
// 0xDD: NTSC M, PAL M,N
// 0xCD: NTSC J
// 0xDC: PAL B,D,G,H,I, COMB N, SECAM
// 0xA6: NTSC M (macro-vision)
// 0xAE: PAL B,D,G,H,I, COMB N (macro-vision)
#define HAGC_REG 0x04
#define HAGC_DEFAULT 0xDD
#define HAGC 0xDD
// Y/C output control, 0x07
// [7] reserved
// [6] swap Cb/Cr outputs
// 0: don't swap Cb/Cr
// 1: (default) swap Cb/Cr
// [5:4] control the blue screen mode
// 00: disabled
// 01: enabled
// 10: auto (default)
// 11: reserved
// [3:0] 2's complement number, controls the output delay between luma and chroma.
// Negative values shift luma outputs to the left while positive valus shift luma
// values to the right. The range is [-5, 7]. Default=000.
#define YC_OPCTRL_REG 0x07
#define YC_OPCTRL_DEFAULT 0x20
#define YC_OPCTRL 0x22
// Luma contrast, 0x08 (internal use)
//
// Luma brightness, 0x09
// offset by -32
//
// Chroma saturation, 0x0a
//
// Chroma Hue phase, 0x0B
// 2's complement number
//
// Chroma AGC, 0x0C
#define CONTRAST_REG 0x08
#define CONTRAST_DEFAULT 0x80
#define BRIGHT_REG 0x09
#define BRIGHT_DEFAULT 0x20
#define SAT_REG 0x0A
#define SAT_DEFAULT 0x80
#define HUE_REG 0x0B
#define HUE_DEFAULT 0x00
#define CHROMA_AGC_REG 0x0C
#define CHROMA_AGC_DEFAULT 0x8A
#define CONTRAST 0x80
#ifdef _640_234 //AT_VGA
#define BRIGHT 0x18
#else
#define BRIGHT 0x20
#endif
#define SAT 0x80
#define HUE 0x00
#define CHROMA_AGC 0x8A
// AGC peak nomial, 0x10
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