-- ----------------------------------------------------------------- Module: filter---- Generated by MATLAB(R) 7.1 and the Filter Design HDL Coder 1.3.---- Generated on: 2008-09-18 15:50:50---- --------------------------------------------------------------- --------------------------------------------------------------- HDL Code Generation Options:---- TargetLanguage: VHDL-- LoopUnrolling: On-- InlineConfigurations: Off-- SafeZeroConcat: Off-- TestBenchStimulus: impulse step ramp chirp noise ---- Filter Settings:---- Discrete-Time FIR Filter (real)-- --------------------------------- Filter Structure  : Direct-Form FIR-- Filter Length     : 11-- Stable            : Yes-- Linear Phase      : Yes (Type 1)-- -------------------------------------------------------------LIBRARY IEEE;USE IEEE.std_logic_1164.all;USE IEEE.numeric_std.ALL;ENTITY filter IS   PORT( clk                             :   IN    std_logic;          clk_enable                      :   IN    std_logic;          reset                           :   IN    std_logic;          filter_in                       :   IN    real; -- double         filter_out                      :   OUT   real  -- double         );END filter;------------------------------------------------------------------Module Architecture: filter----------------------------------------------------------------ARCHITECTURE rtl OF filter IS  -- Local Functions  -- Type Definitions  TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF real; -- double  -- Constants  CONSTANT coeff1                         : real := 8.3272776231721121E-002; -- double  CONSTANT coeff2                         : real := 1.0484690200768515E-001; -- double  CONSTANT coeff3                         : real := -8.9048494270514519E-002; -- double  CONSTANT coeff4                         : real := -1.8648244537178607E-001; -- double  CONSTANT coeff5                         : real := 3.8511245516584115E-002; -- double  CONSTANT coeff6                         : real := 2.2212725756818322E-001; -- double  CONSTANT coeff7                         : real := 3.8511245516584115E-002; -- double  CONSTANT coeff8                         : real := -1.8648244537178607E-001; -- double  CONSTANT coeff9                         : real := -8.9048494270514519E-002; -- double  CONSTANT coeff10                        : real := 1.0484690200768515E-001; -- double  CONSTANT coeff11                        : real := 8.3272776231721121E-002; -- double  -- Signals  SIGNAL delay_pipeline                   : delay_pipeline_type(0 TO 10) := (0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); -- double  SIGNAL product11                        : real := 0.0; -- double  SIGNAL product10                        : real := 0.0; -- double  SIGNAL product9                         : real := 0.0; -- double  SIGNAL product8                         : real := 0.0; -- double  SIGNAL product7                         : real := 0.0; -- double  SIGNAL product6                         : real := 0.0; -- double  SIGNAL product5                         : real := 0.0; -- double  SIGNAL product4                         : real := 0.0; -- double  SIGNAL product3                         : real := 0.0; -- double  SIGNAL product2                         : real := 0.0; -- double  SIGNAL product1                         : real := 0.0; -- double  SIGNAL sum1                             : real := 0.0; -- double  SIGNAL sum2                             : real := 0.0; -- double  SIGNAL sum3                             : real := 0.0; -- double  SIGNAL sum4                             : real := 0.0; -- double  SIGNAL sum5                             : real := 0.0; -- double  SIGNAL sum6                             : real := 0.0; -- double  SIGNAL sum7                             : real := 0.0; -- double  SIGNAL sum8                             : real := 0.0; -- double  SIGNAL sum9                             : real := 0.0; -- double  SIGNAL sum10                            : real := 0.0; -- double  SIGNAL output_register                  : real := 0.0; -- doubleBEGIN  -- Block Statements  Delay_Pipeline_process : PROCESS (clk, reset)  BEGIN    IF reset = '1' THEN      delay_pipeline(0 TO 10) <= (OTHERS => 0.0000000000000000E+000);    ELSIF clk'event AND clk = '1' THEN      IF clk_enable = '1' THEN        delay_pipeline(0) <= filter_in;        delay_pipeline(1 TO 10) <= delay_pipeline(0 TO 9);      END IF;    END IF;   END PROCESS Delay_Pipeline_process;  product11 <= delay_pipeline(10) * coeff11;  product10 <= delay_pipeline(9) * coeff10;  product9 <= delay_pipeline(8) * coeff9;  product8 <= delay_pipeline(7) * coeff8;  product7 <= delay_pipeline(6) * coeff7;  product6 <= delay_pipeline(5) * coeff6;  product5 <= delay_pipeline(4) * coeff5;  product4 <= delay_pipeline(3) * coeff4;  product3 <= delay_pipeline(2) * coeff3;  product2 <= delay_pipeline(1) * coeff2;  product1 <= delay_pipeline(0) * coeff1;  sum1 <= product1 + product2;  sum2 <= sum1 + product3;  sum3 <= sum2 + product4;  sum4 <= sum3 + product5;  sum5 <= sum4 + product6;  sum6 <= sum5 + product7;  sum7 <= sum6 + product8;  sum8 <= sum7 + product9;  sum9 <= sum8 + product10;  sum10 <= sum9 + product11;  Output_Register_process : PROCESS (clk, reset)  BEGIN    IF reset = '1' THEN      output_register <= 0.0000000000000000E+000;    ELSIF clk'event AND clk = '1' THEN      IF clk_enable = '1' THEN        output_register <= sum10;      END IF;    END IF;   END PROCESS Output_Register_process;  -- Assignment Statements  filter_out <= output_register;END rtl;