module control_slave_interface(
						// avalon slave interface
						slave_reset_n,
			//			slave_irq,
						slave_clk,
						slave_chipselect,
						slave_write_n,
						slave_read_n,
						slave_address,
						slave_writedata,
						slave_readdata,	
						// control output
						control_reg,
						dma_source_reg,
						dma_modules_reg,
						dma_current_reg,
					);
input			slave_reset_n;
input			slave_clk;
input			slave_chipselect;
input			slave_write_n;
input			slave_read_n;
input	[ 1:0]	slave_address;
input	[31:0]	slave_writedata;
output	[31:0]	slave_readdata;
//output			slave_irq;

output	[31:0]	control_reg;
output	[31:0]	dma_source_reg;
output	[31:0]	dma_modules_reg;
input	[31:0]	dma_current_reg;

reg		[31:0]	control_reg;
reg		[31:0]	dma_source_reg;
reg		[31:0]	dma_modules_reg;
reg		[31:0]	slave_readdata;

/* ---------------------------------------------------------------------------------
slave interface
--------------------------------------------------------------------------------- */
always @(posedge slave_clk or negedge slave_reset_n)
begin
	if(slave_reset_n == 0)
	begin
		control_reg				<=	0;
		dma_source_reg			<=	0;
		dma_modules_reg			<=	0;
	end
	else if(slave_chipselect && ~slave_write_n)
	begin
		case(slave_address)
		2'b00:	control_reg				<=	slave_writedata;	
		2'b01:	dma_source_reg			<=	slave_writedata;
		2'b10:	dma_modules_reg			<=	slave_writedata;
		endcase
	end 
end

always @(posedge slave_clk or negedge slave_reset_n)
begin
	if(slave_reset_n == 0)
	begin
		slave_readdata	<=	0;
	end
	else if(slave_chipselect && ~slave_read_n)
	begin
		case(slave_address)
		2'b00:	slave_readdata	<=	control_reg;
		2'b01:	slave_readdata	<=	dma_source_reg;
		2'b10:	slave_readdata	<=	dma_modules_reg;
		2'b11:	slave_readdata	<=	dma_current_reg;
		endcase
	end
end
endmodule