module lcd_fifo_control(
						clk,
						reset_n,
						fifo_wrclk,
						fifo_wrreq,
						fifo_wrdata,
						fifo_rdclk,
						fifo_rdreq,
						fifo_rddata,
						fifo_wrusedw,
						fifo_has_room,
						fifo_has_data,
						fifo_rdempty,
						fifo_wrfull,
						cntr_reg_go_bit,
						fifo_is_ready,
						clear_the_fifo,
						fifo_read_clk,
						//test
						//fifo_q,
						);
						
parameter UPLIMIT	= 3084;	
parameter DOWNLIMIT	= 512;	
parameter FIFO_DEPTH= 4096;

input			cntr_reg_go_bit;
input			clk;
input			reset_n;
input			fifo_wrclk;
input			fifo_wrreq;
input	[31:0]	fifo_wrdata;
input			fifo_rdclk;
input			fifo_rdreq;
output	[15:0]	fifo_rddata;
output	[11:0]	fifo_wrusedw;
output			fifo_has_room;
output			fifo_has_data;
output			fifo_rdempty;
output			fifo_wrfull;
output			fifo_is_ready;
output			clear_the_fifo;
output			fifo_read_clk;
//output	[31:0]	fifo_q;

reg				fifo_has_room;
reg				fifo_has_data;
reg				fifo_has_room_reg1;
reg				fifo_has_data_reg1;
wire	[31:0]	fifo_q;
reg				fifo_read_clk;
wire			fifo_read_req;
reg				clear_the_fifo_reg1;
reg				clear_the_fifo_reg2;
wire			clear_the_fifo;
wire			fifo_cleared;		
reg		[5:0]	fifo_preClk_counter;
reg				fifo_preClk_ena;
reg				fifo_preClk_done;
//wire			fifo_is_ready;
reg				fifo_is_ready;
reg				fifo_is_ready_reg1;

always @(posedge fifo_rdclk or negedge reset_n)
begin
	if(reset_n == 0)
	begin
		fifo_preClk_counter	<=	0;
		fifo_preClk_ena		<=	0;
		fifo_preClk_done	<=	0;
	end
//	else if((cntr_reg_go_bit & fifo_cleared) == 1)
	else if(fifo_has_data)
	begin
		if(fifo_preClk_counter == 2)
		begin
			fifo_preClk_ena		<=	0;
			fifo_preClk_done	<=	1;
		end
		else
		begin
			fifo_preClk_ena		<=	1;
			fifo_preClk_done	<=	0;
			fifo_preClk_counter	<=	fifo_preClk_counter + 1;
		end
	end
	else
	begin
		fifo_preClk_ena		<=	0;
		fifo_preClk_done	<=	0;
		fifo_preClk_counter	<=	0;
	end
end

//assign	fifo_is_ready	=	fifo_preClk_done;
/*
  # This is our signal that the fifo has fallen below the write threshold, and
  # should be written with some data as soon as possible.  We double register
  # it to avoid any possible clock-crossing metastability issues.
*/
always @(posedge clk or negedge reset_n)
begin
	if(reset_n == 0)	
		fifo_has_room	<=	0;
	else if(fifo_is_ready)	
		fifo_has_room <= fifo_has_room_reg1;
end
always @(posedge clk or negedge reset_n)
begin
	if(reset_n == 0)	
		fifo_has_room_reg1	<=	0;
	else if(fifo_is_ready) 
		fifo_has_room_reg1 <= (fifo_wrusedw < UPLIMIT);
end
/*
  # This is our signal that the fifo has reached the read threshold
  # and we can start reading out of it.  We double register it to
  # avoid any possible clock-crossing metastability issues.
*/
always @(posedge fifo_rdclk or negedge reset_n)
begin
	if(reset_n == 0)	
		fifo_has_data	<=	0;
	else if(fifo_is_ready) 
		fifo_has_data <= fifo_has_data_reg1;
end
always @(posedge fifo_rdclk or negedge reset_n)
begin
	if(reset_n == 0)	
		fifo_has_data_reg1	<=	0;
	else if(fifo_is_ready) 
		fifo_has_data_reg1 <= (fifo_wrusedw > DOWNLIMIT);
end

//generate the fifo_aclr signal which is used to clear the fifo before the dma goes

always @(posedge fifo_rdclk or negedge reset_n)
begin
	if(reset_n == 0)	
		clear_the_fifo_reg1	<=	0;
	else	
		clear_the_fifo_reg1	<=	clear_the_fifo_reg2 ;			
end

always @(posedge fifo_rdclk or negedge reset_n)
begin
	if(reset_n == 0)	
		clear_the_fifo_reg2	<=	0;
	else	
		clear_the_fifo_reg2	<=	cntr_reg_go_bit ;			
end

assign	clear_the_fifo	=	clear_the_fifo_reg1 ^ clear_the_fifo_reg2;
assign	fifo_cleared	=	clear_the_fifo_reg1 & cntr_reg_go_bit;
//assign	fifo_is_ready	=	fifo_cleared;

always @(posedge fifo_rdclk or negedge reset_n)
begin
	if(reset_n == 0)
		fifo_is_ready	<=	0;
	else
		fifo_is_ready	<=	fifo_is_ready_reg1;
end

always @(posedge fifo_rdclk or negedge reset_n)
begin
	if(reset_n == 0)
		fifo_is_ready_reg1	<=	0;
	else
		fifo_is_ready_reg1	<=	fifo_cleared;
end
//generate the fifo_read_clk signal which is half of fifo_rdclk
always @(posedge fifo_rdclk or negedge reset_n)
begin
	if(reset_n == 0)
		fifo_read_clk	<=	0;
	else if(fifo_rdreq | fifo_preClk_ena)
		fifo_read_clk	<=	~fifo_read_clk;
end

assign	fifo_rddata	=	fifo_read_clk ? fifo_q[15:0] : fifo_q[31:16];
assign	fifo_read_req	=	fifo_rdreq | fifo_preClk_ena;

lcd_fifo	lcd_fifo_0(
				.aclr		(clear_the_fifo),
				.data		(fifo_wrdata),
				.rdclk		(fifo_read_clk),
				.rdreq		(fifo_rdreq),
				.wrclk		(fifo_wrclk),
				.wrreq		(fifo_wrreq),
				.q			(fifo_q),
				.rdempty	(fifo_rdempty),
				.wrfull		(fifo_wrfull),
				.wrusedw	(fifo_wrusedw)
				);
endmodule