/* ---------------------------------------------------------------------------------
tft timing generate module
--------------------------------------------------------------------------------- */
module tft_timing(
						fifo_rdreq,
						fifo_rddata,			//32bit data
						go_bit,					
						tft_clk,				//input 25MHz clock
						tft_reset_n,
						fifo_has_data,
						// tft LCD interface
						oPCLK,					//pixel clock for lcd
						oHSYNC,					//horizontal sync signal
						oVSYNC,					//vertical sync signal
						oDENA,					//data enable signal
						oPDATA,					//18bit pixel datas
						oSC						//scan direction control signal
					);						

parameter LINES     = 480;	// Number of lines
parameter COLUMNS 	= 640;	// Pixel Number Per Line
parameter THFP      = 16;	// Horizontal Front Porch(DCLK)
parameter THBP      = 144;	// Horizontal Back Porch(DCLK)
parameter TWHL     	= 96;	// Horizontal Low Width(DCLK)
parameter TVFP      = 10;	// Vertical Front Porch(HD)
parameter TVBP      = 35;	// Vertical Back Porch(HD)
parameter TWVL     	= 2;	// Vertical Low Width(HD)
/*
parameter LINES     = 6;	// Number of lines
parameter COLUMNS 	= 8;	// Pixel Number Per Line
parameter THFP      = 1;	// Horizontal Front Porch(DCLK)
parameter THBP      = 4;	// Horizontal Back Porch(DCLK)
parameter TWHL     	= 2;	// Horizontal Low Width(DCLK)
parameter TVFP      = 1;	// Vertical Front Porch(HD)
parameter TVBP      = 4;	// Vertical Back Porch(HD)
parameter TWVL     	= 2;	// Vertical Low Width(HD)
*/

output			fifo_rdreq;
input	[15:0]	fifo_rddata;
input			go_bit;
input			tft_reset_n;
input			tft_clk;
input			fifo_has_data;

output			oPCLK;
output			oHSYNC;
output			oVSYNC;
output			oDENA;
output	[17:0]	oPDATA;
output			oSC;

reg				oHSYNC;
reg				oVSYNC;
reg				oDENA;
reg				lineENA;
reg		[9:0]	cCounter;
reg		[9:0]	lCounter;
reg				fifo_rdreq;

reg				go_bit_tft;
reg				go_bit_tft_reg1;
reg				tft_start;

assign oSC		= 	1;
assign oPCLK 	= 	tft_clk;
assign oPDATA 	=	{fifo_rddata[15:11],1'b0,fifo_rddata[10:0],1'b0};

always @(posedge tft_clk or negedge tft_reset_n)
begin
	if(tft_reset_n == 0)	go_bit_tft	<=	0;
	else	go_bit_tft	<=	go_bit_tft_reg1;
end

always @(posedge tft_clk or negedge tft_reset_n)
begin
	if(tft_reset_n == 0)	go_bit_tft_reg1	<=	0;
	else	go_bit_tft_reg1	<=	go_bit;
end

always @(posedge tft_clk or negedge tft_reset_n)
begin
	if(tft_reset_n == 0)	tft_start	<=	0;
	else	tft_start	<=	(tft_start & go_bit_tft) | (fifo_has_data & go_bit_tft);
end

//horizontal sync signal generator
always @(posedge tft_clk or negedge tft_reset_n)
begin
	if(tft_reset_n == 0)	//reset active
	begin
		oDENA					<=	0;
		oHSYNC					<=	0;
		cCounter		[9:0]	<=	0;
		fifo_rdreq				<=	0;
	end
	else if(tft_start == 1)
	begin
		case(cCounter)
		0:			begin	
						oHSYNC		<=	0;
						cCounter	<=	cCounter + 1;	
					end
		TWHL - 1:	begin
						oHSYNC		<=	1;
						cCounter	<=	cCounter + 1;		
					end
		THBP - 2:	begin	//generate the fifo read request signal,
							//sets earlier for 1 clock than oDENA
						fifo_rdreq	<=	lineENA & tft_start;
						cCounter	<=	cCounter + 1;
					end
		THBP - 1:	begin
						//fifo_rdreq	<=	lineENA & tft_start;
						oDENA		<=	lineENA & tft_start; 	//only when lineENA active then oDENA active
						cCounter	<=	cCounter + 1;	
					end
		THBP + COLUMNS - 2:
					begin	//fifo read request signal ends earlier for 1 clock than oDENA
						fifo_rdreq	<=	0;
						cCounter	<=	cCounter + 1;
					end
		THBP + COLUMNS - 1:
					begin	
						//fifo_rdreq	<=	0;
						oDENA		<=	0;
						cCounter	<=	cCounter + 1;	
					end
		THBP + COLUMNS + THFP - 1:
					begin
						oHSYNC		<=	0;
						cCounter	<=	0;
					end
		default:	cCounter	<=	cCounter + 1;	
		endcase
	end
end

//vertical sync signal generator
always @(negedge oHSYNC or negedge tft_reset_n)
begin
	if(tft_reset_n == 0)	//reset active
	begin
		lineENA					<=	0;
		oVSYNC					<=	0;
		lCounter		[9:0]	<=	0;
	end
	else if(tft_start)
	begin
		case(lCounter)
		0:			begin
						oVSYNC		<=	0;
						lCounter	<=	lCounter + 1;
					end
		TWVL - 1:	begin
						oVSYNC		<=	1;
						lCounter	<=	lCounter + 1;
					end
		TVBP - 1:	begin
						lineENA		<=	1;
						lCounter	<=	lCounter + 1;
					end
		TVBP + LINES - 1:
					begin
						lineENA		<=	0;
						lCounter	<=	lCounter + 1;
					end
		TVBP + LINES + TVFP - 1:
					begin
						oVSYNC		<=	0;
						lCounter	<=	0;
					end
		default:	lCounter	<=	lCounter + 1;
		endcase	
	end
end
endmodule