?? top.map.rpt
字號:
Analysis & Synthesis report for top
Sun Mar 02 17:40:47 2008
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. State Machine - |top1|top:inst|transfer:u3|state
8. State Machine - |top1|top:inst|reciever:u2|state
9. General Register Statistics
10. Multiplexer Restructuring Statistics (Restructuring Performed)
11. Source assignments for top:inst|baud:u1
12. Source assignments for top:inst|reciever:u2
13. Source assignments for top:inst|transfer:u3
14. Parameter Settings for User Entity Instance: top:inst|reciever:u2
15. Parameter Settings for User Entity Instance: top:inst|transfer:u3
16. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Mar 02 17:40:47 2008 ;
; Quartus II Version ; 6.0 Build 202 06/20/2006 SP 1 SJ Full Version ;
; Revision Name ; top ;
; Top-level Entity Name ; top1 ;
; Family ; Cyclone ;
; Total logic elements ; 193 ;
; Total pins ; 3 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
+-----------------------------+-----------------------------------------------+
+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP1C6Q240C8 ; ;
; Top-level entity name ; top1 ; top ;
; Family name ; Cyclone ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M512 Memory Blocks ; Unlimited ; Unlimited ;
; Maximum Number of M4K Memory Blocks ; Unlimited ; Unlimited ;
; Maximum Number of M-RAM Memory Blocks ; Unlimited ; Unlimited ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
+--------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+------------------------------+
; top1.bdf ; yes ; User Block Diagram/Schematic File ; F:/UARTEXAMPLE/top1.bdf ;
; baud.vhd ; yes ; User VHDL File ; F:/UARTEXAMPLE/baud.vhd ;
; reciever.vhd ; yes ; User VHDL File ; F:/UARTEXAMPLE/reciever.vhd ;
; top.vhd ; yes ; User VHDL File ; F:/UARTEXAMPLE/top.vhd ;
; transfer.vhd ; yes ; User VHDL File ; F:/UARTEXAMPLE/transfer.vhd ;
+----------------------------------+-----------------+------------------------------------+------------------------------+
+---------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-----------------------+
; Resource ; Usage ;
+---------------------------------------------+-----------------------+
; Total logic elements ; 193 ;
; -- Combinational with no register ; 61 ;
; -- Register only ; 9 ;
; -- Combinational with a register ; 123 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 60 ;
; -- 3 input functions ; 19 ;
; -- 2 input functions ; 101 ;
; -- 1 input functions ; 4 ;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -