library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity reciever is
    generic(framlenr:integer:=8); 
         
    Port (bclkr,resetr,rxdr:in std_logic;                           --定義輸入輸出信號
          r_ready:out std_logic;
          rbuf:out std_logic_vector(7 downto 0));
end reciever;
 
architecture behavioral of reciever is

type states is (r_start,r_center,r_wait,r_sample,r_stop);               --定義各子狀態
signal state:states:=r_start;
signal rxd_sync:std_logic;
begin
pro1:process(rxdr)
begin
  if rxdr='0' then
     rxd_sync<='0';
  else rxd_sync<='1';
  end if;
end process;
 
pro2:process(bclkr,resetr,rxd_sync)                            --主控時序、組合進程
variable count:std_logic_vector(3 downto 0);                    --定義中間變量
variable rcnt:integer:=0;
variable rbufs:std_logic_vector(7 downto 0);
begin
  if resetr='1' then                                          --復位
     state<=r_start; count:="0000";
  elsif rising_edge(bclkr) then
     case state is
           when r_start=>if rxd_sync='0' then
                            state<=r_center; r_ready<='0'; rcnt:=0;
                                     else state<=r_start; r_ready<='0';
                                     end if;                              --狀態1，等待起始位
       when r_center=>if rxd_sync='0' then
                                            if count="0100" then state<=r_wait; count:="0000";
                                            else count:=count+1; state<=r_center;
                                            end if;
                                     else state<=r_start;
                                     end if;                              --狀態2，求出每位的中點
       when r_wait=>if count>="1110" then
                            if rcnt=framlenr then state<=r_stop;
                                            else state<=r_sample;
                                            end if;
                                        count:="0000";                    --狀態3，等待狀態
                         else count:=count+1; state<=r_wait;
                                     end if;
       when r_sample=>rbufs(rcnt):=rxd_sync; rcnt:=rcnt+1;
                         state<=r_wait;                                    --狀態4，數據位采樣檢測
       when r_stop=>r_ready<='1'; rbuf<=rbufs;
                         state<=r_start;                                   --狀態4，輸出幀接收完畢信號
       when others=>state<=r_start;
     end case;
  end if;
end process;
end behavioral;