OHCI_TD		ENDS

;<AMI_SHDR_START>
;----------------------------------------------------------------------------
; Name:		OHCI_TD_CONTROL
;
; Description:	Bit definition for OHCI_TD ControlStatus field
;
; Fields:	 Name		Type		Description
;		------------------------------------------------------------
;		Reserved	BITS:17-00	Reserved bits
;		BufferRounding	BITS:18		Buffer rounding (1-Allow small packets)
;		DirectionPid	BITS:20-19	Direction & PID (SETUP/IN/OUT etc)
;		DelayInt	BITS:23-21	Num. frames to wait before interrupting
;		DataToggle	BITS:25-24	Data toggle
;		ErrorCount	BITS:27-26	Error count
;		ConditionCode	BITS:31-28	Completion condition code
;
;----------------------------------------------------------------------------
;<AMI_SHDR_END>


; Bit definition for general transfer descriptor control fields
;-------------------------------------------------------------------------
GTD_BUFFER_ROUNDING		EQU	000040000h
GTD_DIRECTION_PID		EQU	000180000h
	GTD_SETUP_PACKET	EQU	000000000h
	GTD_OUT_PACKET		EQU	000080000h
	GTD_IN_PACKET		EQU	000100000h
GTD_DELAY_INTERRUPT		EQU	000e00000h
	GTD_IntD		EQU	000000000h	; depend on device,now guest 0
GTD_DATA_TOGGLE			EQU	003000000h
	GTD_SETUP_TOGGLE	EQU	002000000h	; same as MSB of data toggle
	GTD_DATA1_TOGGLE	EQU	003000000h
	GTD_STATUS_TOGGLE	EQU	003000000h
GTD_ERROR_COUNT			EQU	00c000000h
	GTD_NO_ERRORS		EQU	000000000h
	GTD_ONE_ERROR		EQU	004000000h
	GTD_TWO_ERRORS		EQU	008000000h
	GTD_THREE_ERRORS	EQU	00C000000h
GTD_CONDITION_CODE		EQU	0f0000000h
;-------------------------------------------------------------------------

; Bit define for ConditionCode or CompletionCode use for each CallBack func
; transmission error
;-------------------------------------------------------------------------
GTD_STATUS_FIELD		EQU	0f0000000h ;include NOT_ACCESS
GTD_NO_ERROR			EQU	00h
GTD_CRC_ERROR			EQU	01h
GTD_BIT_STUFF			EQU	02h
GTD_TOGGLE_MISMATCH		EQU	03h
GTD_STALL			EQU	04h
GTD_DEVICE_NOT_RESPOND		EQU	05h
GTD_PID_CHECK_ERROR		EQU	06h
GTD_UNEXPECTED_PID		EQU	07h
GTD_DATA_OVERRUN		EQU	08h
GTD_DATA_UNDERRUN		EQU	09h
GTD_BUFFER_OVERRUN		EQU	0ch 		; not used for GTD
GTD_BUFFER_UNDERRUN		EQU	0dh 		; not used for GTD
GTD_NOT_ACCESSED		EQU	0fh
;-------------------------------------------------------------------------

; Equates for Host Controller Operational Register
; reg for control and status
;-------------------------------------------------------------------------
OHCI_REVISION_REG		EQU	00h
OHCI_CONTROL_REG		EQU	04h
OHCI_COMMAND_STATUS		EQU	08h
OHCI_INTERRUPT_STATUS		EQU	0ch
OHCI_INTERRUPT_ENABLE		EQU	10h
OHCI_INTERRUPT_DISABLE		EQU	14h
; reg for memory pointer
OHCI_HCCA_REG			EQU	18h
OHCI_PERIOD_CURRENT_ED		EQU	1ch
OHCI_CONTROL_HEAD_ED		EQU	20h
OHCI_CONTROL_CURRENT_ED		EQU	24h
OHCI_BULK_HEAD_ED		EQU	28h
OHCI_BULK_CURRENT_ED		EQU	2ch
OHCI_DONE_HEAD			EQU	30h
; reg for frame counter
OHCI_FRAME_INTERVAL		EQU	34h
OHCI_FRAME_REMAINING		EQU	38h
OHCI_FRAME_NUMBER		EQU	3ch
OHCI_PERIODIC_START		EQU	40h
OHCI_LS_THRESHOLD		EQU	44h
; reg for root hub
OHCI_RH_DESCRIPTOR_A		EQU	48h
OHCI_RH_DESCRIPTOR_B		EQU	4ch
OHCI_RH_STATUS			EQU	50h
OHCI_RH_PORT1_STATUS		EQU	54h
OHCI_RH_PORT2_STATUS		EQU	58h

; OHCI emulation register equates
OHCI_HCE_CONTROL		EQU	100h
OHCI_HCE_INPUT			EQU	104h
OHCI_HCE_OUTPUT			EQU	108h
OHCI_HCE_STATUS			EQU	10Ch

; Bit definitions for emulation registers
HCE_CNTRL_EMULATION_ENABLE	EQU	BIT0
HCE_CNTRL_EMULATION_INTERRUPT	EQU	BIT1
HCE_CNTRL_CHARACTER_PENDING	EQU	BIT2
HCE_CNTRL_IRQ_ENABLE		EQU	BIT3
HCE_CNTRL_EXT_IRQ_ENABLE	EQU	BIT4
HCE_CNTRL_GA20_SEQ		EQU	BIT5
HCE_CNTRL_IRQ1_ACTIVE		EQU	BIT6
HCE_CNTRL_IRQ12_ACTIVE		EQU	BIT7
HCE_CNTRL_A20_STATE		EQU	BIT8


HCE_STS_OUTPUTFULL		EQU	BIT0
HCE_STS_INPUTFULL		EQU	BIT1
HCE_STS_FLAG			EQU	BIT2
HCE_STS_CMDDATA			EQU	BIT3
HCE_STS_INHIBIT_SWITCH		EQU	BIT4
HCE_STS_AUXOUTPUTFULL		EQU	BIT5
HCE_STS_TIMEOUT			EQU	BIT6
HCE_STS_PARITY			EQU	BIT7
;-------------------------------------------------------------------------

; Bit define for HC control register
;-------------------------------------------------------------------------
CONTROL_BULK_RATE		EQU	0003h
PERIODIC_LIST_ENABLE		EQU	0004h
ISOCHRONOUS_ENABLE		EQU	0008h
CONTROL_LIST_ENABLE		EQU	0010h
BULK_LIST_ENABLE		EQU	0020h
HC_FUNCTION_STATE		EQU	00c0h
	USBRESET		EQU	0000h
	USBRESUME		EQU	0040h
	USBOPERATIONAL		EQU	0080h
	USBSUSPEND		EQU	00c0h
INTERRUPT_ROUTING		EQU	0100h
REMOTE_WAKEUP_CONNECT		EQU	0200h
REMOTE_WAKEUP_ENABLE		EQU	0400h
;-------------------------------------------------------------------------

; Bit define for HC command status register
;-------------------------------------------------------------------------
HC_RESET			EQU	00001h
CONTROL_LIST_FILLED		EQU	00002h
BULK_LIST_FILLED		EQU	00004h
OWNERSHIP_CHANGE_REQUEST	EQU	00008h
SCHEDULING_OVERRUN_COUNT	EQU	30000h
									
; Bit define for HC interrupt status register
;-------------------------------------------------------------------------
SCHEDULING_OVERRUN		EQU	00000001h
WRITEBACK_DONEHEAD		EQU	00000002h
START_OF_FRAME			EQU	00000004h
RESUME_DETECTED			EQU	00000008h
UNCOVERABLE_ERR			EQU	00000010h
FRAMENUMBER_OVERFLOW		EQU	00000020h
RH_STATUS_CHANGE		EQU	00000040h
OWNERSHIP_CHANGE		EQU	40000000h

; Bit define for HC interrupt enable register
;-------------------------------------------------------------------------
SCHEDULING_OVERRUN_ENABLE	EQU	00000001h
WRITEBACK_DONEHEAD_ENABLE	EQU	00000002h
START_OF_FRAME_ENABLE		EQU	00000004h
RESUME_DETECTED_ENABLE		EQU	00000008h
UNCOVERABLE_ERR_ENABLE		EQU	00000010h
FRAMENUMBER_OVERFLOW_ENABLE	EQU	00000020h
RH_STATUS_CHANGE_ENABLE		EQU	00000040h
OWNERSHIP_CHANGE_ENABLE		EQU	40000000h
MASTER_INTERRUPT_ENABLE		EQU	80000000h

; Bit define for HC interrupt disable register
;-------------------------------------------------------------------------
SCHEDULING_OVERRUN_DISABLE	EQU	00000001h
WRITEBACK_DONEHEAD_DISABLE	EQU	00000002h
START_OF_FRAME_DISABLE		EQU	00000004h
RESUME_DETECTED_DISABLE		EQU	00000008h
UNCOVERABLE_ERR_DISABLE		EQU	00000010h
FRAMENUMBER_OVERFLOW_DISABLE	EQU	00000020h
RH_STATUS_CHANGE_DISABLE	EQU	00000040h
OWNERSHIP_CHANGE_DISABLE	EQU	40000000h
MASTER_INTERRUPT_DISABLE	EQU	80000000h

; Bit define for HC frame interval register
;-------------------------------------------------------------------------
FRAME_INTERVAL			EQU	00003fffh
FS_LARGEST_DATA_PACKET		EQU	4fff0000h
FRAME_INTERVAL_TOGGLE		EQU	80000000h

; Bit define for HC frame remaining register
;-------------------------------------------------------------------------
FRAME_REMAINING			EQU	00003fffh
FRAME_REMAINING_TOGGLE		EQU	80000000h

; Bit define for HC root hub descriptor A register
;-------------------------------------------------------------------------
RH_PORT_NUMBER			EQU	000000ffh
POWER_SWITCH_MODE		EQU	00000100h
NO_POWER_SWITCH			EQU	00000200h
DEVICE_TYPE			EQU	00000400h
OVERCURRENT_PROTECT		EQU	00000800h
NO_OVERCURRENT_PROTECT		EQU	00001000h
POWERON2POWERGOOD_TIME		EQU	0ff000000h


; Bit define for HC root hub descriptor B register
;-------------------------------------------------------------------------
DEVICE_REMOVABLE		EQU	0000ffffh
PORT_POWER_MASK			EQU	0ffff0000h

; Bit define for HC root hub status register
;-------------------------------------------------------------------------
LOCAL_POWER_STATUS		EQU	00000001h
CLEAR_GLOBAL_POWER		EQU	00000001h
OVERCURRENT			EQU	00000002h
DEVICE_REMOTE_WAKEUP		EQU	00008000h
SET_REMOTE_WAKEUP		EQU	00008000h
LOCAL_POWER_CHANGE		EQU	00010000h
SET_GLOBAL_POWER		EQU	00010000h
OVERCURRENT_CHANGE		EQU	00020000h
CLEAR_REMOTE_WAKEUP		EQU	80000000h
					  
; Bit define for HC root hub port1,2 status register
;-------------------------------------------------------------------------
CURRENT_CONNECT_STATUS		EQU	00000001h
CLEAR_PORT_ENABLE		EQU	00000001h
PORT_ENABLE_STATUS		EQU	00000002h
SET_PORT_ENABLE			EQU	00000002h
PORT_SUSPEND_STATUS		EQU	00000004h
SET_PORT_SUSPEND		EQU	00000004h
PORT_OVERCURRENT		EQU	00000008h
CLEAR_PORT_SUSPEND		EQU	00000004h
PORT_RESET_STATUS		EQU	00000010h
SET_PORT_RESET			EQU	00000010h
PORT_POWER_STATUS		EQU	00000100h
SET_PORT_POWER			EQU	00000100h
LOW_SPEED_DEVICE_ATTACHED	EQU	00000200h
CLEAR_PORT_POWER		EQU	00000200h
CONNECT_STATUS_CHANGE		EQU	00010000h
PORT_ENABLE_STATUS_CHANGE	EQU	00020000h
PORT_SUSPEND_STATUS_CHANGE	EQU	00040000h
PORT_OVERCURRENT_CHANGE		EQU	00080000h
PORT_RESET_STATUS_CHANGE	EQU	00100000h
;-------------------------------------------------------------------------
;***************************************************************************;
;***************************************************************************;
;**                                                                       **;
;**           (C)Copyright 1985-2002, American Megatrends, Inc.           **;
;**                                                                       **;
;**                          All Rights Reserved.                         **;
;**                                                                       **;
;**                6145-F Northbelt Pkwy, Norcross, GA 30071              **;
;**                                                                       **;
;**                          Phone (770)-246-8600                         **;
;**                                                                       **;
;***************************************************************************;
;***************************************************************************;