/* * Network device driver for the MACE ethernet controller on * Apple Powermacs.  Assumes it's under a DBDMA controller. * * Copyright (C) 1996 Paul Mackerras. */#ifdef MODULE#include <linux/module.h>#include <linux/version.h>#endif#include <linux/kernel.h>#include <linux/netdevice.h>#include <linux/etherdevice.h>#include <linux/delay.h>#include <linux/string.h>#include <linux/timer.h>#include <asm/prom.h>#include <asm/dbdma.h>#include <asm/io.h>#include <asm/pgtable.h>#include "mace.h"#ifdef MODULEstatic struct device *mace_devs = NULL;#endif#define N_RX_RING	8#define N_TX_RING	6#define MAX_TX_ACTIVE	1#define NCMDS_TX	1	/* dma commands per element in tx ring */#define RX_BUFLEN	(ETH_FRAME_LEN + 8)#define TX_TIMEOUT	HZ	/* 1 second *//* Bits in transmit DMA status */#define TX_DMA_ERR	0x80struct mace_data {    volatile struct mace *mace;    volatile struct dbdma_regs *tx_dma;    int tx_dma_intr;    volatile struct dbdma_regs *rx_dma;    int rx_dma_intr;    volatile struct dbdma_cmd *tx_cmds;	/* xmit dma command list */    volatile struct dbdma_cmd *rx_cmds;	/* recv dma command list */    struct sk_buff *rx_bufs[N_RX_RING];    int rx_fill;    int rx_empty;    struct sk_buff *tx_bufs[N_TX_RING];    int tx_fill;    int tx_empty;    unsigned char maccc;    unsigned char tx_fullup;    unsigned char tx_active;    unsigned char tx_bad_runt;    struct net_device_stats stats;    struct timer_list tx_timeout;    int timeout_active;};/* * Number of bytes of private data per MACE: allow enough for * the rx and tx dma commands plus a branch dma command each, * and another 16 bytes to allow us to align the dma command * buffers on a 16 byte boundary. */#define PRIV_BYTES	(sizeof(struct mace_data) \	+ (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))static int bitrev(int);static int mace_open(struct device *dev);static int mace_close(struct device *dev);static int mace_xmit_start(struct sk_buff *skb, struct device *dev);static struct net_device_stats *mace_stats(struct device *dev);static void mace_set_multicast(struct device *dev);static void mace_reset(struct device *dev);static int mace_set_address(struct device *dev, void *addr);static void mace_interrupt(int irq, void *dev_id, struct pt_regs *regs);static void mace_txdma_intr(int irq, void *dev_id, struct pt_regs *regs);static void mace_rxdma_intr(int irq, void *dev_id, struct pt_regs *regs);static void mace_set_timeout(struct device *dev);static void mace_tx_timeout(unsigned long data);static inline void dbdma_reset(volatile struct dbdma_regs *dma);static inline void mace_clean_rings(struct mace_data *mp);static void __mace_set_address(struct device *dev, void *addr);/* * If we can't get a skbuff when we need it, we use this area for DMA. */static unsigned char dummy_buf[RX_BUFLEN+2];/* Bit-reverse one byte of an ethernet hardware address. */static inline intbitrev(int b){    int d = 0, i;    for (i = 0; i < 8; ++i, b >>= 1)	d = (d << 1) | (b & 1);    return d;}intmace_probe(struct device *dev){	int j, rev;	struct mace_data *mp;	struct device_node *mace;	unsigned char *addr;	static int maces_found = 0;	static struct device_node *next_mace;	if (!maces_found) {		next_mace = find_devices("mace");		maces_found = 1;	}	mace = next_mace;	if (mace == 0)		return -ENODEV;	next_mace = mace->next;	if (mace->n_addrs != 3 || mace->n_intrs != 3) {		printk(KERN_ERR "can't use MACE %s: expect 3 addrs and 3 intrs\n",		       mace->full_name);		return -ENODEV;	}	if (dev == NULL)		dev = init_etherdev(0, PRIV_BYTES);	else {		dev->priv = kmalloc(PRIV_BYTES, GFP_KERNEL);		if (dev->priv == 0)			return -ENOMEM;	}	memset(dev->priv, 0, PRIV_BYTES);	mp = (struct mace_data *) dev->priv;	dev->base_addr = mace->addrs[0].address;	mp->mace = (volatile struct mace *)		ioremap(mace->addrs[0].address, 0x1000);	dev->irq = mace->intrs[0].line;	addr = get_property(mace, "mac-address", NULL);	if (addr == NULL) {		addr = get_property(mace, "local-mac-address", NULL);		if (addr == NULL) {			printk(KERN_ERR "Can't get mac-address for MACE at %lx\n",			       dev->base_addr);			return -EAGAIN;		}	}	printk(KERN_INFO "%s: MACE at", dev->name);	rev = addr[0] == 0 && addr[1] == 0xA0;	for (j = 0; j < 6; ++j) {		dev->dev_addr[j] = rev? bitrev(addr[j]): addr[j];		printk("%c%.2x", (j? ':': ' '), dev->dev_addr[j]);	}	printk(", chip revision %d.%d\n",		in_8(&mp->mace->chipid_hi), in_8(&mp->mace->chipid_lo));	mp = (struct mace_data *) dev->priv;	mp->maccc = ENXMT | ENRCV;	mp->tx_dma = (volatile struct dbdma_regs *)		ioremap(mace->addrs[1].address, 0x1000);	mp->tx_dma_intr = mace->intrs[1].line;	mp->rx_dma = (volatile struct dbdma_regs *)		ioremap(mace->addrs[2].address, 0x1000);	mp->rx_dma_intr = mace->intrs[2].line;	mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);	mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;	memset(&mp->stats, 0, sizeof(mp->stats));	memset((char *) mp->tx_cmds, 0,	       (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));	init_timer(&mp->tx_timeout);	mp->timeout_active = 0;	dev->open = mace_open;	dev->stop = mace_close;	dev->hard_start_xmit = mace_xmit_start;	dev->get_stats = mace_stats;	dev->set_multicast_list = mace_set_multicast;	dev->set_mac_address = mace_set_address;	ether_setup(dev);	mace_reset(dev);	if (request_irq(dev->irq, mace_interrupt, 0, "MACE", dev)) {		printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);		return -EAGAIN;	}	if (request_irq(mace->intrs[1].line, mace_txdma_intr, 0, "MACE-txdma",			dev)) {		printk(KERN_ERR "MACE: can't get irq %d\n", mace->intrs[1].line);		return -EAGAIN;	}	if (request_irq(mace->intrs[2].line, mace_rxdma_intr, 0, "MACE-rxdma",			dev)) {		printk(KERN_ERR "MACE: can't get irq %d\n", mace->intrs[2].line);		return -EAGAIN;	}	return 0;}static void dbdma_reset(volatile struct dbdma_regs *dma){    int i;    out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);    /*     * Yes this looks peculiar, but apparently it needs to be this     * way on some machines.     */    for (i = 200; i > 0; --i)	if (ld_le32(&dma->control) & RUN)	    udelay(1);}static void mace_reset(struct device *dev){    struct mace_data *mp = (struct mace_data *) dev->priv;    volatile struct mace *mb = mp->mace;    int i;    /* soft-reset the chip */    i = 200;    while (--i) {	out_8(&mb->biucc, SWRST);	if (in_8(&mb->biucc) & SWRST) {	    udelay(10);	    continue;	}	break;    }    if (!i) {	printk(KERN_ERR "mace: cannot reset chip!\n");	return;    }    out_8(&mb->imr, 0xff);	/* disable all intrs for now */    i = in_8(&mb->ir);    out_8(&mb->maccc, 0);	/* turn off tx, rx */    out_8(&mb->biucc, XMTSP_64);    out_8(&mb->utr, RTRD);    out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);    out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */    out_8(&mb->rcvfc, 0);    /* load up the hardware address */    __mace_set_address(dev, dev->dev_addr);    /* clear the multicast filter */    out_8(&mb->iac, ADDRCHG | LOGADDR);    while ((in_8(&mb->iac) & ADDRCHG) != 0)	;    for (i = 0; i < 8; ++i) {	out_8(&mb->ladrf, 0);    }    /* done changing address */    out_8(&mb->iac, 0);    out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);}static void __mace_set_address(struct device *dev, void *addr){    volatile struct mace *mb = ((struct mace_data *) dev->priv)->mace;    unsigned char *p = addr;    int i;    /* load up the hardware address */    out_8(&mb->iac, ADDRCHG | PHYADDR);    while ((in_8(&mb->iac) & ADDRCHG) != 0)	;    for (i = 0; i < 6; ++i)	out_8(&mb->padr, dev->dev_addr[i] = p[i]);}static int mace_set_address(struct device *dev, void *addr){    struct mace_data *mp = (struct mace_data *) dev->priv;    volatile struct mace *mb = mp->mace;    unsigned long flags;    save_flags(flags); cli();    __mace_set_address(dev, addr);    out_8(&mb->iac, 0);    /* note: setting ADDRCHG clears ENRCV */    out_8(&mb->maccc, mp->maccc);    restore_flags(flags);    return 0;}static int mace_open(struct device *dev){    struct mace_data *mp = (struct mace_data *) dev->priv;    volatile struct mace *mb = mp->mace;    volatile struct dbdma_regs *rd = mp->rx_dma;    volatile struct dbdma_regs *td = mp->tx_dma;    volatile struct dbdma_cmd *cp;    int i;    struct sk_buff *skb;    unsigned char *data;    /* reset the chip */    mace_reset(dev);    /* initialize list of sk_buffs for receiving and set up recv dma */    mace_clean_rings(mp);    memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd));    cp = mp->rx_cmds;    for (i = 0; i < N_RX_RING - 1; ++i) {	skb = dev_alloc_skb(RX_BUFLEN + 2);	if (skb == 0) {	    data = dummy_buf;	} else {	    skb_reserve(skb, 2);	/* so IP header lands on 4-byte bdry */	    data = skb->data;	}	mp->rx_bufs[i] = skb;	st_le16(&cp->req_count, RX_BUFLEN);	st_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);	st_le32(&cp->phy_addr, virt_to_bus(data));	cp->xfer_status = 0;	++cp;    }    mp->rx_bufs[i] = 0;    st_le16(&cp->command, DBDMA_STOP);    mp->rx_fill = i;    mp->rx_empty = 0;    /* Put a branch back to the beginning of the receive command list */    ++cp;    st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);    st_le32(&cp->cmd_dep, virt_to_bus(mp->rx_cmds));    /* start rx dma */    out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */    out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds));    out_le32(&rd->control, (RUN << 16) | RUN);    /* put a branch at the end of the tx command list */    cp = mp->tx_cmds + NCMDS_TX * N_TX_RING;    st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);    st_le32(&cp->cmd_dep, virt_to_bus(mp->tx_cmds));    /* reset tx dma */    out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);    out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds));    mp->tx_fill = 0;    mp->tx_empty = 0;    mp->tx_fullup = 0;    mp->tx_active = 0;    mp->tx_bad_runt = 0;    /* turn it on! */    out_8(&mb->maccc, mp->maccc);    /* enable all interrupts except receive interrupts */    out_8(&mb->imr, RCVINT);#ifdef MOD_INC_USE_COUNT    MOD_INC_USE_COUNT;#endif    return 0;}static inline void mace_clean_rings(struct mace_data *mp){    int i;    /* free some skb's */    for (i = 0; i < N_RX_RING; ++i) {	if (mp->rx_bufs[i] != 0) {	    dev_kfree_skb(mp->rx_bufs[i]);	    mp->rx_bufs[i] = 0;	}    }    for (i = mp->tx_empty; i != mp->tx_fill; ) {	dev_kfree_skb(mp->tx_bufs[i]);	if (++i >= N_TX_RING)	    i = 0;    }}static int mace_close(struct device *dev){    struct mace_data *mp = (struct mace_data *) dev->priv;    volatile struct mace *mb = mp->mace;    volatile struct dbdma_regs *rd = mp->rx_dma;    volatile struct dbdma_regs *td = mp->tx_dma;    /* disable rx and tx */    out_8(&mb->maccc, 0);    out_8(&mb->imr, 0xff);		/* disable all intrs */    /* disable rx and tx dma */    st_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */    st_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */    mace_clean_rings(mp);#ifdef MOD_DEC_USE_COUNT    MOD_DEC_USE_COUNT;#endif    return 0;}static inline void mace_set_timeout(struct device *dev){    struct mace_data *mp = (struct mace_data *) dev->priv;    unsigned long flags;    save_flags(flags);    cli();    if (mp->timeout_active)	del_timer(&mp->tx_timeout);    mp->tx_timeout.expires = jiffies + TX_TIMEOUT;    mp->tx_timeout.function = mace_tx_timeout;    mp->tx_timeout.data = (unsigned long) dev;    add_timer(&mp->tx_timeout);    mp->timeout_active = 1;    restore_flags(flags);}static int mace_xmit_start(struct sk_buff *skb, struct device *dev){    struct mace_data *mp = (struct mace_data *) dev->priv;    volatile struct dbdma_regs *td = mp->tx_dma;    volatile struct dbdma_cmd *cp, *np;    unsigned long flags;    int fill, next, len;    /* see if there's a free slot in the tx ring */    save_flags(flags); cli();    fill = mp->tx_fill;    next = fill + 1;    if (next >= N_TX_RING)	next = 0;    if (next == mp->tx_empty) {	dev->tbusy = 1;	mp->tx_fullup = 1;	restore_flags(flags);	return 1;		/* can't take it at the moment */    }    restore_flags(flags);    /* partially fill in the dma command block */    len = skb->len;    if (len > ETH_FRAME_LEN) {	printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len);	len = ETH_FRAME_LEN;    }    mp->tx_bufs[fill] = skb;    cp = mp->tx_cmds + NCMDS_TX * fill;    st_le16(&cp->req_count, len);