?? sync.vhd
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--
-- Copyright (C) 2003 by J. Kearney, Bolton, Massachusetts
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
library unisim;
use unisim.vcomponents.all;
entity Sync is
Port ( RESET : in std_logic;
REQ : in std_logic;
ACK : in std_logic;
STATUS : buffer std_logic);
end sync;
architecture RTL of sync is
signal acked : std_logic;
begin
process (reset, req, status, acked)
begin
if (reset = '1') or (acked = '1') then
status <= '0';
elsif rising_edge(req) then
status <= '1';
end if;
end process;
process (req, status, ack)
begin
if status = '0' then
acked <= '0';
elsif rising_edge(ack) then
acked <= '1';
end if;
end process;
end RTL;
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