library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

library unisim;
use unisim.vcomponents.all;

entity ClkMux is
    Port ( RESET : in std_logic;
	 		  A : in std_logic;
           B : in std_logic;
           sel : in std_logic;
           O : out std_logic);
end ClkMux;

architecture RTL of ClkMux is

	signal D1, Q1, D2, Q2 : std_logic;

begin

	FF1: FDC port map (CLR => RESET, C => A, D => D1, Q => Q1);
	FF2: FDC port map (CLR => RESET, C => B, D => D2, Q => Q2);

	D1 <= (not sel) and (not Q2);
	D2 <= sel and (not Q1);

	O <= (A and Q1) or (B and Q2);


end RTL;