?? sdi.c
字號:
//SDICCON CmdIndex [7:0] = 0X4c : CMD12
//SDICCON Command Start(CMST) [8 ] = 1 : command start
//SDICCON WaitRsp [9 ] = 1 : wait_resp
//SDICCON LongRsp [10 ] = 0 : short response
rSDICCON=(0x1<<9)|(0x1<<8)|0x4c; //sht_resp, wait_resp, start, CMD12
//-- Check end of CMD12
if(!Chk_CMDend(12, 1))
goto STRCMD12;
//rSDICSTA=0xa00; // Clear cmd_end(with rsp)
/*
//-- Display Rx data
Uart_Printf("\nRx data\n");
for(i=0;i<128*2;i++)
{
if(Rx_buffer[i] != Tx_buffer[i])
{
Uart_Printf("%08x, %08x\n",Tx_buffer[i], Rx_buffer[i]);
break;
}
}
*/
Uart_Printf("\n--End stream read test\n");
}
/*****************************************
寫存儲塊函數
函數名: Wt_Block
描述: 通過三種方式寫存儲塊
返回值：void
*****************************************/
void Wt_Block(void)
{
U32 mode;
int status;
wt_cnt=0;
Uart_Printf("[Block write test]\n");
RE1:
Uart_Printf("0:Polling write 1:Interrupt write 2:DMA write\nSelect the test mode?");
mode=(U32)Uart_GetIntNum();
Uart_Printf("\n");
if(mode>2)
goto RE1;
//SDICON FIFO Reset (FRST) [1] = 1 : FIFO reset
rSDICON |= rSDICON|(1<<1); // FIFO reset
// mode=1;//tark
if(mode!=2)
//SDIDCON BlkNum [11: 0] = block : Block Number (0~4095).
//SDIDCON Data Transfer Mode (DatMode) [13:12] = 3 : data transmit start
//SDIDCON Stop by force (STOP) [14 ] = 1 : stop by force
//SDIDCON DMA Enable(EnDMA) [15 ] = 1 : dma enable,
//SDIDCON Wide bus enable (WideBus) [16 ] = 0 : standard bus mode(only SDIDAT[0] used),
//SDIDCON Block mode (BlkMode) [17 ] = 1 : block data transfer
//SDIDCON Busy AfterCommand(BACMD) [18 ] = 0 : directly after DatMode set,
//SDIDCON Receive After Command (RACMD) [19 ] = 1 : Rx after cmd
//SDIDCON Transmit After Response(TARSP) [20 ] = 1 : after response receive(assume DatMode sets to 2’b11)
//SDIDCON SDIO InterruptPeriodType(PrdType)[21 ] = 0 : exactly 2 cycle,
rSDIDCON=(1<<20)|(1<<17)|(Wide<<16)|(3<<12)|(block<<0);
//SDICARG CmdArg [31:0] = 0 : Command Argument
rSDICARG=0x0; // CMD24/25(addr)
REWTCMD:
switch(mode)
{
case POL:
if(block<2) // SINGLE_WRITE
{
//SDICCON CmdIndex [7:0] = 0X58 : CMD24
//SDICCON Command Start(CMST) [8 ] = 1 : command start
//SDICCON WaitRsp [9 ] = 1 : wait_resp
//SDICCON LongRsp [10 ] = 0 : short response
rSDICCON=(0x1<<9)|(0x1<<8)|0x58; //sht_resp, wait_resp, dat, start, CMD24
if(!Chk_CMDend(24, 1)) //-- Check end of CMD24
goto REWTCMD;
}
else // MULTI_WRITE
{
//SDICCON CmdIndex [7:0] = 0X59 : CMD25
//SDICCON Command Start(CMST) [8 ] = 1 : command start
//SDICCON WaitRsp [9 ] = 1 : wait_resp
//SDICCON LongRsp [10 ] = 0 : short response
rSDICCON=(0x1<<9)|(0x1<<8)|0x59; //sht_resp, wait_resp, dat, start, CMD25
if(!Chk_CMDend(25, 1)) //-- Check end of CMD25
goto REWTCMD;
}
//rSDICSTA=0xa00; // Clear cmd_end(with rsp)
while(wt_cnt<128*block)
{
status=rSDIFSTA;
if((status&0x2000)==0x2000)
{
rSDIDAT=*Tx_buffer++;
wt_cnt++;
}
}
break;
case INT:
pISR_SDI=(unsigned)Wt_Int;
//INTMSK INT_SDI [21] = 0 : service available,
rINTMSK = ~(BIT_SDI);
//SDIIMSK TFHalf InterruptEnable [4] = 1 : Tx FIFO half int
rSDIIMSK=0x10;
if(block<2) // SINGLE_WRITE
{
//SDICCON CmdIndex [7:0] = 0X58 : CMD24
//SDICCON Command Start(CMST) [8 ] = 1 : command start
//SDICCON WaitRsp [9 ] = 1 : wait_resp
//SDICCON LongRsp [10 ] = 0 : short response
rSDICCON=(0x1<<9)|(0x1<<8)|0x58;
if(!Chk_CMDend(24, 1)) //-- Check end of CMD24
goto REWTCMD;
}
else // MULTI_WRITE
{
//SDICCON CmdIndex [7:0] = 0X59 : CMD25
//SDICCON Command Start(CMST) [8 ] = 1 : command start
//SDICCON WaitRsp [9 ] = 1 : wait_resp
//SDICCON LongRsp [10 ] = 0 : short response
rSDICCON=(0x1<<9)|(0x1<<8)|0x59;
if(!Chk_CMDend(25, 1)) //-- Check end of CMD25
goto REWTCMD;
}
//rSDICSTA=0xa00; // Clear cmd_end(with rsp)
while(!TR_end);
//while(wt_cnt<128);
//INTMSK INT_SDI [21] = 0 : service available,
rINTMSK |= (BIT_SDI);
TR_end=0;
//SDIIMSK SDI interrupt mask register [17: 0] = 0 : All mask
rSDIIMSK=0; // All mask
break;
case DMA:
pISR_DMA0=(unsigned)DMA_end;
//INTMSK INT_DMA0 [17] = 0 : Service availa
rINTMSK = ~(BIT_DMA0);
//DISRC0 S_ADDR [30:0] = Tx_buffer : Tx_buffer
rDISRC0=(int)(Tx_buffer);
//DISRCC0 INC [0] = 0 : inc
//DISRCC0 LOC [1] = 0 : AHB
rDISRCC0=(0<<1)+(0<<0); // AHB, inc
rDIDST0=(U32)(SDIDAT); // SDIDAT
//DIDSTC0 INC [0] = 1 : fix
//DIDSTC0 LOC [1] = 1 : APB
rDIDSTC0=(1<<1)+(1<<0); // APB, fix
//DCON0 TC [19: 0] = 128*block: Initial transfer count (or transfer beat).
//DCON0 DSZ [21:20] = 10 : Word
//DCON0 RELOAD [22 ] = 1 : auto-reload of
//DCON0 SWHW_SEL [23 ] = 1 : H/W request
//DCON0 HWSRCSEL [26:24] = 10 : SDI
//DCON0 SERVMODE [27 ] = 0 : single service
//DCON0 TSZ [28 ] = 0 : single tx
//DCON0 INT [29 ] = 1 : TC int
//DCON0 SYNC [30 ] = 0 : sync PCLK
//DCON0 DMD_HS [31 ] = 1 : handshake
rDCON0=(1<<31)+(0<<30)+(1<<29)+(0<<28)+(0<<27)+(2<<24)+(1<<23)+(1<<22)+(2<<20)+128*block;
//DMASKTRIG0 SW_TRIG [0] = 0 : no-sw trigger
//DMASKTRIG0 ON_OFF [1] = 1 : DMA2 channel on
//DMASKTRIG0 STOP [2] = 0 : no-stop
rDMASKTRIG0=(0<<2)+(1<<1)+0;
//SDIDCON BlkNum [11: 0] = block : Block Number (0~4095).
//SDIDCON Data Transfer Mode (DatMode) [13:12] = 3 : data transmit start
//SDIDCON Stop by force (STOP) [14 ] = 1 : stop by force
//SDIDCON DMA Enable(EnDMA) [15 ] = 1 : dma enable,
//SDIDCON Wide bus enable (WideBus) [16 ] = 0 : standard bus mode(only SDIDAT[0] used),
//SDIDCON Block mode (BlkMode) [17 ] = 1 : block data transfer
//SDIDCON Busy AfterCommand(BACMD) [18 ] = 0 : directly after DatMode set,
//SDIDCON Receive After Command (RACMD) [19 ] = 1 : Rx after cmd
//SDIDCON Transmit After Response(TARSP) [20 ] = 1 : after response receive(assume DatMode sets to 2’b11)
//SDIDCON SDIO InterruptPeriodType(PrdType)[21 ] = 0 : exactly 2 cycle,
rSDIDCON=(1<<20)|(1<<17)|(Wide<<16)|(1<<15)|(3<<12)|(block<<0);
// Tx after rsp, blk, 4bit bus, dma enable, Tx start, blk num
if(block<2) // SINGLE_WRITE
{
//SDICCON CmdIndex [7:0] = 0X58 : CMD24
//SDICCON Command Start(CMST) [8 ] = 1 : command start
//SDICCON WaitRsp [9 ] = 1 : wait_resp
//SDICCON LongRsp [10 ] = 0 : short response
rSDICCON=(0x1<<9)|(0x1<<8)|0x58; //sht_resp, wait_resp, dat, start, CMD24
if(!Chk_CMDend(24, 1)) //-- Check end of CMD24
goto REWTCMD;
}
else // MULTI_WRITE
{
//SDICCON CmdIndex [7:0] = 0X59 : CMD25
//SDICCON Command Start(CMST) [8 ] = 1 : command start
//SDICCON WaitRsp [9 ] = 1 : wait_resp
//SDICCON LongRsp [10 ] = 0 : short response
rSDICCON=(0x1<<9)|(0x1<<8)|0x59; //sht_resp, wait_resp, dat, start, CMD25
if(!Chk_CMDend(25, 1)) //-- Check end of CMD25
goto REWTCMD;
}
//rSDICSTA=0xa00; // Clear cmd_end(with rsp)
while(!TR_end);
//INTMSK BIT_DMA0 [17] = 1 : MASK
rINTMSK |= (BIT_DMA0);
TR_end=0;
//DMASKTRIG0 STOP [2] = 1 : DMA0 stop
rDMASKTRIG0=(1<<2); //DMA0 stop
break;
default:
break;
}
//-- Check end of DATA
if(!Chk_DATend())
Uart_Printf("dat error\n");
//SDIDSTA Rx Data Progress On (RxDatOn) [0 ] R : Data receive in progress.
//SDIDSTA Tx Data progress On (TxDatOn) [1 ] R : Data transmit in progress.
//SDIDSTA Start Bit Error (SbitErr) [2 ] =0 : not detect,
//SDIDSTA Busy Finish (BusyFin) [3 ] =0 : not detect,
//SDIDSTA Data Transfer Finish (DatFin) [4 ] =1 : data finish detect
//SDIDSTA Data Time Out (DatTout) [5 ] =0 : not detect,
//SDIDSTA Data Receive CRC Fail (DatCrc)[6 ] =0 : not detect,
//SDIDSTA CRC Status Fail(CrcSta) [7 ] =0 : not detect,
//SDIDSTA FIFO Fail error (FFfail) [8 ] =0 : not detect,
//SDIDSTA SDIO InterruptDetect(IOIntDet)[9 ] =0 : not detect,
//SDIDSTA Data Time Out (DatTout) [10] =0 : not occur,
rSDIDSTA=0x10;
if(block>1)
{
//--Stop cmd(CMD12)
REWCMD12:
//SDIDCON BlkNum [11: 0] = block : Block Number (0~4095).
//SDIDCON Data Transfer Mode (DatMode) [13:12] = 1 : only busy check start
//SDIDCON Stop by force (STOP) [14 ] = 0 : normal
//SDIDCON DMA Enable(EnDMA) [15 ] = 0 : disable(polling),
//SDIDCON Wide bus enable (WideBus) [16 ] = 0 : standard bus mode(only SDIDAT[0] used),
//SDIDCON Block mode (BlkMode) [17 ] = 1 : blk
//SDIDCON Busy AfterCommand(BACMD) [18 ] = 1 : after command sent (assume DatMode sets to 2’b01)
//SDIDCON Receive After Command (RACMD) [19 ] = 1 : Rx after cmd
//SDIDCON Transmit After Response(TARSP) [20 ] = 0 : directly after DatMode set,
//SDIDCON SDIO InterruptPeriodType(PrdType)[21 ] = 0 : exactly 2 cycle,
rSDIDCON=(1<<18)|(1<<17)|(0<<16)|(1<<12)|(block<<0);
//--Stop cmd(CMD12)
//SDICARG CmdArg [31:0] = 0 : Command Argument
rSDICARG=0x0; //CMD12(stuff bit)
//SDICCON CmdIndex [7:0] = 0X4c : CMD12
//SDICCON Command Start(CMST) [8 ] = 1 : command start
//SDICCON WaitRsp [9 ] = 1 : wait_resp
//SDICCON LongRsp [10 ] = 0 : short response
rSDICCON=(0x1<<9)|(0x1<<8)|0x4c; //sht_resp, wait_resp, start, CMD12
//-- Check end of CMD12
if(!Chk_CMDend(12, 1))
goto REWCMD12;
//rSDICSTA=0xa00; // Clear cmd_end(with rsp)
//-- Check end of DATA(with busy state)
if(!Chk_BUSYend())
Uart_Printf("error\n");
//SDIDSTA Rx Data Progress On (RxDatOn) [0 ] R : Data receive in progress.
//SDIDSTA Tx Data progress On (TxDatOn) [1 ] R : Data transmit in progress.
//SDIDSTA Start Bit Error (SbitErr) [2 ] =0 : not detect,
//SDIDSTA Busy Finish (BusyFin) [3 ] =1 : busy finish detect
//SDIDSTA Data Transfer Finish (DatFin) [4 ] =0 : not detect,
//SDIDSTA Data Time Out (DatTout) [5 ] =0 : not detect,
//SDIDSTA Data Receive CRC Fail (DatCrc)[6 ] =0 : not detect,
//SDIDSTA CRC Status Fail(CrcSta) [7 ] =0 : not detect,
//SDIDSTA FIFO Fail error (FFfail) [8 ] =0 : not detect,
//SDIDSTA SDIO InterruptDetect(IOIntDet)[9 ] =0 : not detect,
//SDIDSTA Data Time Out (DatTout) [10] =0 : not occur,
rSDIDSTA=0x08;
}
}
void Wt_Stream(void) // only for MMC, 3blk write
{
int status, wt_cnt=0;
if(MMC!=1)
{
Uart_Printf("Stream write command supports only MMC!\n");
return;
}
Uart_Printf("\n[Stream write test]\n");
RECMD20:
//SDIDCON BlkNum [11: 0] = block : Block Number (0~4095).
//SDIDCON Data Transfer Mode (DatMode) [13:12] = 3 : data transmit start
//SDIDCON Stop by force (STOP) [14 ] = 1 : stop by force
//SDIDCON DMA Enable(EnDMA) [15 ] = 1 : dma enable,
//SDIDCON Wide bus enable (WideBus) [16 ] = 0 : standard bus mode(only SDIDAT[0] used),
//SDIDCON Block mode (BlkMode) [17 ] = 0 : stream data transfer,
//SDIDCON Busy AfterCommand(BACMD) [18 ] = 0 : directly after DatMode set,
//SDIDCON Receive After Command (RACMD) [19 ] = 1 : Rx after cmd
//SDIDCON Transmit After Response(TARSP) [20 ] = 1 : after response receive(assume DatMode sets to 2’b11)
//SDIDCON SDIO InterruptPeriodType(PrdType)[21 ] = 0 : exactly 2 cycle,
rSDIDCON=(1<<20)|(0<<17)|(0<<16)|(3<<12); // stream mode
//SDICARG CmdArg [31:0] = 0 : Command Argument
rSDICARG=0x0; // CMD20(addr)
//SDICCON CmdIndex [7:0] = 0X54 : CMD20
//SDICCON Command Start(CMST) [8 ] = 1 : command start
//SDICCON WaitRsp [9 ] = 1 : wait_resp
//SDICCON LongRsp [10 ] = 0 : short response
rSDICCON=(0x1<<9)|(0x1<<8)|0x54; //sht_resp, wait_resp, dat, start, CMD20
//-- Check end of CMD25
if(!Chk_CMDend(20, 1))
goto RECMD20;
//rSDICSTA=0xa00; // Clear cmd_end(with rsp)
while(wt_cnt<128*block)
{
status=rSDIFSTA;
if((status&0x2000)==0x2000)
//SDIDAT Data Register [31:0] This field contains the data to be transmitted or received over the SDI channel.
rSDIDAT=Tx_buffer[wt_cnt++];
}
//-- Check end of DATA
while( rSDIFSTA&0x400 );
Delay(10); // for the empty of DATA line(Hardware)
//SDIDCON BlkNum [11: 0] = block : Block Number (0~4095).
//SDIDCON Data Transfer Mode (DatMode) [13:12] = 0 : ready,
//SDIDCON Stop by force (STOP) [14 ] = 1 : stop by force
//SDIDCON DMA Enable(EnDMA) [15 ] = 1 : dma enable,
//SDIDCON Wide bus enable (WideBus) [16 ] = 0 : standard bus mode(only SDIDAT[0] used),
//SDIDCON Block mode (BlkMode) [17 ] = 0 : stream data transfer,
//SDIDCON Busy AfterCommand(BACMD) [18 ] = 0 : directly after DatMode set,
//SDIDCON Receive After Command (RACMD) [19 ] = 1 : Rx after cmd
//SDIDCON Transmit After Response(TARSP) [20 ] = 1 : after response receive(assume DatMode sets to 2’b11)
//SDIDCON SDIO InterruptPeriodType(PrdType)[21 ] = 0 : exactly 2 cycle,
rSDIDCON=(1<<20)|(0<<17)|(0<<16)|(1<<14)|(0<<12);
while( (rSDIDSTA&0x3)!=0x0 );
if(rSDIDSTA!=0)
Uart_Printf("rSDIDSTA=0x%x\n", rSDIDSTA);
//SDIDSTA Rx Data Progress On (RxDatOn) [0 ] R : Data receive in progress.
//SDIDSTA Tx Data progress On (TxDatOn) [1 ] R : Data transmit in progress.
//SDIDSTA Start Bit Error (SbitErr) [2 ] =1 : command end
//SDIDSTA Busy Finish (BusyFin) [3 ] =1 : busy finish detect
//SDIDSTA Data Transfer Finish (DatFin) [4 ] =1 : data finish detect
//SDIDSTA Data Time Out (DatTout) [5 ] =1 : timeout
//SDIDSTA Data Receive CRC Fail (DatCrc)[6 ] =1 : receive crc fail
//SDIDSTA CRC Status Fail(CrcSta) [7 ] =1 : crc status fail
//SDIDSTA FIFO Fail error (FFfail) [8 ] =0 : not detect,
//SDIDSTA SDIO InterruptDetect(IOIntDet)[9 ] =0 : not detect,
//SDIDSTA Data Time Out (DatTout) [10] =0 : not occur,
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