return MCBSP_FGETH(hMcbsp,SPCR,XSYNCERR);
}
/*----------------------------------------------------------------------------*/
IDEF Uint32 MCBSP_rsyncerr(MCBSP_Handle hMcbsp) {
  return MCBSP_FGETH(hMcbsp,SPCR,RSYNCERR);
}
/*----------------------------------------------------------------------------*/
IDEF void MCBSP_enableXmt(MCBSP_Handle hMcbsp) {
  MCBSP_FSETSH(hMcbsp,SPCR,XRST,NO);
}
/*----------------------------------------------------------------------------*/
IDEF void MCBSP_enableRcv(MCBSP_Handle hMcbsp) {
  MCBSP_FSETSH(hMcbsp,SPCR,RRST,NO);
}
/*----------------------------------------------------------------------------*/
IDEF void MCBSP_enableFsync(MCBSP_Handle hMcbsp) {
  MCBSP_FSETSH(hMcbsp,SPCR,FRST,NO);
}
/*----------------------------------------------------------------------------*/
IDEF void MCBSP_enableSrgr(MCBSP_Handle hMcbsp) {
  MCBSP_FSETSH(hMcbsp,SPCR,GRST,NO);
}
/*----------------------------------------------------------------------------*/
#if(!C64_SUPPORT) /* ?? added C64_SUPPORT */
IDEF void MCBSP_config(MCBSP_Handle hMcbsp, MCBSP_Config *config) {

  Uint32 gie;
  volatile Uint32 *base = (volatile Uint32 *)(hMcbsp->baseAddr);
  register int x0,x1,x2,x3,x4,x5,x6,x7;

  gie = IRQ_globalDisable();

  /* the compiler generates more efficient code if the loads */
  /* and stores are grouped together rather than intermixed  */
  x0 = config->spcr;
  x1 = config->rcr;
  x2 = config->xcr;
  x3 = config->srgr;
  x4 = config->mcr;
  x5 = config->rcer;
  x6 = config->xcer;
  x7 = config->pcr;

  base[_MCBSP_SPCR_OFFSET] = 0x00000000;
  base[_MCBSP_RCR_OFFSET]  = x1;
  base[_MCBSP_XCR_OFFSET]  = x2;
  base[_MCBSP_SRGR_OFFSET] = x3;
  base[_MCBSP_MCR_OFFSET]  = x4;
  base[_MCBSP_RCER_OFFSET] = x5;
  base[_MCBSP_XCER_OFFSET] = x6;
  base[_MCBSP_PCR_OFFSET]  = x7;
  base[_MCBSP_SPCR_OFFSET] = x0;

  IRQ_globalRestore(gie);
}
#else /* (C64_SUPPORT)*/
IDEF void MCBSP_config(MCBSP_Handle hMcbsp, MCBSP_Config *config) {

  Uint32 gie;
  volatile Uint32 *base = (volatile Uint32 *)(hMcbsp->baseAddr);
  register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13;

  gie = IRQ_globalDisable();

  /* the compiler generates more efficient code if the loads */
  /* and stores are grouped together rather than intermixed  */
  x0  = config->spcr;
  x1  = config->rcr;
  x2  = config->xcr;
  x3  = config->srgr;
  x4  = config->mcr;
  x5  = config->rcere0;
  x6  = config->rcere1;
  x7  = config->rcere2;
  x8  = config->rcere3;
  x9  = config->xcere0;
  x10 = config->xcere1;
  x11 = config->xcere2;
  x12 = config->xcere3;
  x13 = config->pcr;

  base[_MCBSP_SPCR_OFFSET]   = 0x00000000;
  base[_MCBSP_RCR_OFFSET]    = x1;
  base[_MCBSP_XCR_OFFSET]    = x2;
  base[_MCBSP_SRGR_OFFSET]   = x3;
  base[_MCBSP_MCR_OFFSET]    = x4;
  base[_MCBSP_RCERE0_OFFSET] = x5;
  base[_MCBSP_RCERE1_OFFSET] = x6;
  base[_MCBSP_RCERE2_OFFSET] = x7;
  base[_MCBSP_RCERE3_OFFSET] = x8;
  base[_MCBSP_XCERE0_OFFSET] = x9;
  base[_MCBSP_XCERE1_OFFSET] = x10;
  base[_MCBSP_XCERE2_OFFSET] = x11;
  base[_MCBSP_XCERE3_OFFSET] = x12;
  base[_MCBSP_PCR_OFFSET]    = x13;
  base[_MCBSP_SPCR_OFFSET]   = x0;

  IRQ_globalRestore(gie);
}
#endif /* C64_SUPPORT */
/*----------------------------------------------------------------------------*/
#if (!C64_SUPPORT) /* ?? added C64_SUPPORT */
IDEF void MCBSP_configArgs(MCBSP_Handle hMcbsp, Uint32 spcr, Uint32 rcr, 
  Uint32 xcr, Uint32 srgr, Uint32 mcr, Uint32 rcer, Uint32 xcer, Uint32 pcr) {

  Uint32 gie;
  volatile Uint32 *base = (volatile Uint32 *)(hMcbsp->baseAddr);

  gie = IRQ_globalDisable();

  base[_MCBSP_SPCR_OFFSET] = 0x00000000;
  base[_MCBSP_RCR_OFFSET]  = rcr;
  base[_MCBSP_XCR_OFFSET]  = xcr;
  base[_MCBSP_SRGR_OFFSET] = srgr;
  base[_MCBSP_MCR_OFFSET]  = mcr;
  base[_MCBSP_RCER_OFFSET] = rcer;
  base[_MCBSP_XCER_OFFSET] = xcer;
  base[_MCBSP_PCR_OFFSET]  = pcr;
  base[_MCBSP_SPCR_OFFSET] = spcr;

  IRQ_globalRestore(gie);
}
#else /* (C64_SUPPORT) */
IDEF void MCBSP_configArgs(MCBSP_Handle hMcbsp, Uint32 spcr, Uint32 rcr, 
  Uint32 xcr, Uint32 srgr, Uint32 mcr, Uint32 rcere0, Uint32 rcere1, 
  Uint32 rcere2, Uint32 rcere3, Uint32 xcere0, Uint32 xcere1, Uint32 xcere2, 
  Uint32 xcere3, Uint32 pcr) {

  Uint32 gie;
  volatile Uint32 *base = (volatile Uint32 *)(hMcbsp->baseAddr);

  gie = IRQ_globalDisable();

  base[_MCBSP_SPCR_OFFSET]   = 0x00000000;
  base[_MCBSP_RCR_OFFSET]    = rcr;
  base[_MCBSP_XCR_OFFSET]    = xcr;
  base[_MCBSP_SRGR_OFFSET]   = srgr;
  base[_MCBSP_MCR_OFFSET]    = mcr;
  base[_MCBSP_RCERE0_OFFSET] = rcere0;
  base[_MCBSP_RCERE1_OFFSET] = rcere1;
  base[_MCBSP_RCERE2_OFFSET] = rcere2;
  base[_MCBSP_RCERE3_OFFSET] = rcere3;
  base[_MCBSP_XCERE0_OFFSET] = xcere0;
  base[_MCBSP_XCERE1_OFFSET] = xcere1;
  base[_MCBSP_XCERE2_OFFSET] = xcere2;
  base[_MCBSP_XCERE3_OFFSET] = xcere3;
  base[_MCBSP_PCR_OFFSET]    = pcr;
  base[_MCBSP_SPCR_OFFSET]   = spcr;

  IRQ_globalRestore(gie);
}
#endif /* C64_SUPPORT */
/*----------------------------------------------------------------------------*/
#if (!C64_SUPPORT) /* ?? added C64_SUPPORT */
IDEF void MCBSP_getConfig(MCBSP_Handle hMcbsp, MCBSP_Config *config) {

  Uint32 gie;
  volatile Uint32 *base = (volatile Uint32 *)(hMcbsp->baseAddr);
  volatile MCBSP_Config* cfg = (volatile MCBSP_Config*)config;
  register int x0,x1,x2,x3,x4,x5,x6,x7;

  gie = IRQ_globalDisable();

  /* the compiler generates more efficient code if the loads */
  /* and stores are grouped together rather than intermixed  */

  x0 = base[_MCBSP_SPCR_OFFSET];
  x1 = base[_MCBSP_RCR_OFFSET];
  x2 = base[_MCBSP_XCR_OFFSET];
  x3 = base[_MCBSP_SRGR_OFFSET];
  x4 = base[_MCBSP_MCR_OFFSET];
  x5 = base[_MCBSP_RCER_OFFSET];
  x6 = base[_MCBSP_XCER_OFFSET];
  x7 = base[_MCBSP_PCR_OFFSET];

  cfg->spcr = x0;
  cfg->rcr  = x1;
  cfg->xcr  = x2;
  cfg->srgr = x3;
  cfg->mcr  = x4;
  cfg->rcer = x5;
  cfg->xcer = x6;
  cfg->pcr  = x7;

  IRQ_globalRestore(gie);
}
#else /* (C64_SUPPORT) */
IDEF void MCBSP_getConfig(MCBSP_Handle hMcbsp, MCBSP_Config *config) {

  Uint32 gie;
  volatile Uint32 *base = (volatile Uint32 *)(hMcbsp->baseAddr);
  volatile MCBSP_Config* cfg = (volatile MCBSP_Config*)config;
  register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13;

  gie = IRQ_globalDisable();

  /* the compiler generates more efficient code if the loads */
  /* and stores are grouped together rather than intermixed  */

  x0  = base[_MCBSP_SPCR_OFFSET];
  x1  = base[_MCBSP_RCR_OFFSET];
  x2  = base[_MCBSP_XCR_OFFSET];
  x3  = base[_MCBSP_SRGR_OFFSET];
  x4  = base[_MCBSP_MCR_OFFSET];
  x5  = base[_MCBSP_RCERE0_OFFSET];
  x6  = base[_MCBSP_RCERE1_OFFSET];
  x7  = base[_MCBSP_RCERE2_OFFSET];
  x8  = base[_MCBSP_RCERE3_OFFSET];
  x9  = base[_MCBSP_XCERE0_OFFSET];
  x10 = base[_MCBSP_XCERE1_OFFSET];
  x11 = base[_MCBSP_XCERE2_OFFSET];
  x12 = base[_MCBSP_XCERE3_OFFSET];
  x13 = base[_MCBSP_PCR_OFFSET];

  cfg->spcr   = x0;
  cfg->rcr    = x1;
  cfg->xcr    = x2;
  cfg->srgr   = x3;
  cfg->mcr    = x4;
  cfg->rcere0 = x5;
  cfg->rcere1 = x6;
  cfg->rcere2 = x7;
  cfg->rcere3 = x8;
  cfg->xcere0 = x9;
  cfg->xcere1 = x10;
  cfg->xcere2 = x11;
  cfg->xcere3 = x12;
  cfg->pcr    = x13;

  IRQ_globalRestore(gie);
}
#endif /* C64_SUPPORT */
/*----------------------------------------------------------------------------*/
#endif /* USEDEFS */


#endif /* MCBSP_SUPPORT */
#endif /* _CSL_MCBSP_H_ */
/******************************************************************************\
* End of csl_mcbsp.h
\******************************************************************************/