//#include "global.h"#define C_DISABLE		(0)#define C_ENABLE		(1)#define C_DISABLE_CLKCHANGE	(2)#define C_ENABLE_CLKCHANGE	(3)#define C_REENABLE		(4)#define SM501_PANEL_NAME        "SM501 Panel"#define SM501_CRT_NAME          "SM501 CRT"#define SM501_MEM_SIZE	0x1000000#define DEBUG 0/* *  Debug macros  */#if DEBUG#  define DPRINTK(fmt, args...)	printk("%s: " fmt, __FUNCTION__ , ## args)#else#  define DPRINTK(fmt, args...)#endif/* * Minimum X and Y resolutions */#define MIN_XRES	64#define MIN_YRES	64#define SM501_REG_OFFSET 0x0e00000#define SM501_REG_SIZE 0x00200000/* * * Definitions for the System Configuration registers. * */#define SYSTEM_CTRL                                     0x000000#define SYSTEM_CTRL_DPMS                                31:30#define SYSTEM_CTRL_DPMS_VPHP                           0#define SYSTEM_CTRL_DPMS_VPHN                           1#define SYSTEM_CTRL_DPMS_VNHP                           2#define SYSTEM_CTRL_DPMS_VNHN                           3#define SYSTEM_CTRL_PCI_BURST                           29:29#define SYSTEM_CTRL_PCI_BURST_DISABLE                   0#define SYSTEM_CTRL_PCI_BURST_ENABLE                    1#define SYSTEM_CTRL_CSC_STATUS                          28:28#define SYSTEM_CTRL_CSC_STATUS_IDLE                     0#define SYSTEM_CTRL_CSC_STATUS_BUSY                     1#define SYSTEM_CTRL_PCI_MASTER                          25:25#define SYSTEM_CTRL_PCI_MASTER_STOP                     0#define SYSTEM_CTRL_PCI_MASTER_START                    1#define SYSTEM_CTRL_LATENCY_TIMER                       24:24#define SYSTEM_CTRL_LATENCY_TIMER_ENABLE                0#define SYSTEM_CTRL_LATENCY_TIMER_DISABLE               1#define SYSTEM_CTRL_PANEL_STATUS                        23:23#define SYSTEM_CTRL_PANEL_STATUS_CURRENT                0#define SYSTEM_CTRL_PANEL_STATUS_PENDING                1#define SYSTEM_CTRL_VIDEO_STATUS                        22:22#define SYSTEM_CTRL_VIDEO_STATUS_CURRENT                0#define SYSTEM_CTRL_VIDEO_STATUS_PENDING                1#define SYSTEM_CTRL_DE_FIFO                             20:20#define SYSTEM_CTRL_DE_FIFO_NOT_EMPTY                   0#define SYSTEM_CTRL_DE_FIFO_EMPTY                       1#define SYSTEM_CTRL_DE_STATUS                           19:19#define SYSTEM_CTRL_DE_STATUS_IDLE                      0#define SYSTEM_CTRL_DE_STATUS_BUSY                      1#define SYSTEM_CTRL_CRT_STATUS                          17:17#define SYSTEM_CTRL_CRT_STATUS_CURRENT                  0#define SYSTEM_CTRL_CRT_STATUS_PENDING                  1#define SYSTEM_CTRL_ZVPORT                              16:16#define SYSTEM_CTRL_ZVPORT_0                            0#define SYSTEM_CTRL_ZVPORT_1                            1#define SYSTEM_CTRL_PCI_BURST_READ                      15:15#define SYSTEM_CTRL_PCI_BURST_READ_DISABLE              0#define SYSTEM_CTRL_PCI_BURST_READ_ENABLE               1#define SYSTEM_CTRL_DE_ABORT                            13:12#define SYSTEM_CTRL_DE_ABORT_NORMAL                     0#define SYSTEM_CTRL_DE_ABORT_2D_ABORT                   3#define SYSTEM_CTRL_PCI_SUBSYS_LOCK                     11:11#define SYSTEM_CTRL_PCI_SUBSYS_LOCK_DISABLE             0#define SYSTEM_CTRL_PCI_SUBSYS_LOCK_ENABLE              1#define SYSTEM_CTRL_PCI_RETRY                           7:7#define SYSTEM_CTRL_PCI_RETRY_ENABLE                    0#define SYSTEM_CTRL_PCI_RETRY_DISABLE                   1#define SYSTEM_CTRL_PCI_CLOCK_RUN                       6:6#define SYSTEM_CTRL_PCI_CLOCK_RUN_DISABLE               0#define SYSTEM_CTRL_PCI_CLOCK_RUN_ENABLE                1#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE           5:4#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1         0#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2         1#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4         2#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8         3#define SYSTEM_CTRL_CRT_TRISTATE                        2:2#define SYSTEM_CTRL_CRT_TRISTATE_DISABLE                0#define SYSTEM_CTRL_CRT_TRISTATE_ENABLE                 1#define SYSTEM_CTRL_INTMEM_TRISTATE                     1:1#define SYSTEM_CTRL_INTMEM_TRISTATE_DISABLE             0#define SYSTEM_CTRL_INTMEM_TRISTATE_ENABLE              1#define SYSTEM_CTRL_PANEL_TRISTATE                      0:0#define SYSTEM_CTRL_PANEL_TRISTATE_DISABLE              0#define SYSTEM_CTRL_PANEL_TRISTATE_ENABLE               1#define MISC_CTRL                                       0x000004#define MISC_CTRL_PCI_PAD                               31:30#define MISC_CTRL_PCI_PAD_24MA                          0#define MISC_CTRL_PCI_PAD_12MA                          1#define MISC_CTRL_PCI_PAD_8MA                           2#define MISC_CTRL_48_SELECT                             29:28#define MISC_CTRL_48_SELECT_CRYSTAL                     0#define MISC_CTRL_48_SELECT_CPU_96                      2#define MISC_CTRL_48_SELECT_CPU_48                      3#define MISC_CTRL_UART1_SELECT                          27:27#define MISC_CTRL_UART1_SELECT_UART                     0#define MISC_CTRL_UART1_SELECT_SSP                      1#define MISC_CTRL_8051_LATCH                            26:26#define MISC_CTRL_8051_LATCH_DISABLE                    0#define MISC_CTRL_8051_LATCH_ENABLE                     1#define MISC_CTRL_FPDATA                                25:25#define MISC_CTRL_FPDATA_18                             0#define MISC_CTRL_FPDATA_24                             1#define MISC_CTRL_CRYSTAL                               24:24#define MISC_CTRL_CRYSTAL_24                            0#define MISC_CTRL_CRYSTAL_12                            1#define MISC_CTRL_DRAM_REFRESH                          22:21#define MISC_CTRL_DRAM_REFRESH_8                        0#define MISC_CTRL_DRAM_REFRESH_16                       1#define MISC_CTRL_DRAM_REFRESH_32                       2#define MISC_CTRL_DRAM_REFRESH_64                       3#define MISC_CTRL_BUS_HOLD                              20:18#define MISC_CTRL_BUS_HOLD_FIFO_EMPTY                   0#define MISC_CTRL_BUS_HOLD_8                            1#define MISC_CTRL_BUS_HOLD_16                           2#define MISC_CTRL_BUS_HOLD_24                           3#define MISC_CTRL_BUS_HOLD_32                           4#define MISC_CTRL_HITACHI_READY                         17:17#define MISC_CTRL_HITACHI_READY_NEGATIVE                0#define MISC_CTRL_HITACHI_READY_POSITIVE                1#define MISC_CTRL_INTERRUPT                             16:16#define MISC_CTRL_INTERRUPT_NORMAL                      0#define MISC_CTRL_INTERRUPT_INVERT                      1#define MISC_CTRL_PLL_CLOCK_COUNT                       15:15#define MISC_CTRL_PLL_CLOCK_COUNT_DISABLE               0#define MISC_CTRL_PLL_CLOCK_COUNT_ENABLE                1#define MISC_CTRL_DAC_BAND_GAP                          14:13#define MISC_CTRL_DAC_POWER                             12:12#define MISC_CTRL_DAC_POWER_ENABLE                      0#define MISC_CTRL_DAC_POWER_DISABLE                     1#define MISC_CTRL_USB_SLAVE_CONTROLLER                  11:11#define MISC_CTRL_USB_SLAVE_CONTROLLER_CPU              0#define MISC_CTRL_USB_SLAVE_CONTROLLER_8051             1#define MISC_CTRL_BURST_LENGTH                          10:10#define MISC_CTRL_BURST_LENGTH_8                        0#define MISC_CTRL_BURST_LENGTH_1                        1#define MISC_CTRL_USB_SELECT                            9:9#define MISC_CTRL_USB_SELECT_MASTER                     0#define MISC_CTRL_USB_SELECT_SLAVE                      1#define MISC_CTRL_LOOPBACK                              8:8#define MISC_CTRL_LOOPBACK_NORMAL                       0#define MISC_CTRL_LOOPBACK_USB_HOST                     1#define MISC_CTRL_CLOCK_DIVIDER_RESET                   7:7#define MISC_CTRL_CLOCK_DIVIDER_RESET_ENABLE            0#define MISC_CTRL_CLOCK_DIVIDER_RESET_DISABLE           1#define MISC_CTRL_TEST_MODE                             6:5#define MISC_CTRL_TEST_MODE_NORMAL                      0#define MISC_CTRL_TEST_MODE_DEBUGGING                   1#define MISC_CTRL_TEST_MODE_NAND                        2#define MISC_CTRL_TEST_MODE_MEMORY                      3#define MISC_CTRL_NEC_MMIO                              4:4#define MISC_CTRL_NEC_MMIO_30                           0#define MISC_CTRL_NEC_MMIO_62                           1#define MISC_CTRL_CLOCK                                 3:3#define MISC_CTRL_CLOCK_PLL                             0#define MISC_CTRL_CLOCK_TEST                            1#define MISC_CTRL_HOST_BUS                              2:0#define MISC_CTRL_HOST_BUS_HITACHI                      0#define MISC_CTRL_HOST_BUS_PCI                          1#define MISC_CTRL_HOST_BUS_XSCALE                       2#define MISC_CTRL_HOST_BUS_STRONGARM                    4#define MISC_CTRL_HOST_BUS_NEC                          6#define GPIO_MUX_LOW                                    0x000008#define GPIO_MUX_LOW_31                                 31:31#define GPIO_MUX_LOW_31_GPIO                            0#define GPIO_MUX_LOW_31_PWM                             1#define GPIO_MUX_LOW_30                                 30:30#define GPIO_MUX_LOW_30_GPIO                            0#define GPIO_MUX_LOW_30_PWM                             1#define GPIO_MUX_LOW_29                                 29:29#define GPIO_MUX_LOW_29_GPIO                            0#define GPIO_MUX_LOW_29_PWM                             1#define GPIO_MUX_LOW_28                                 28:28#define GPIO_MUX_LOW_28_GPIO                            0#define GPIO_MUX_LOW_28_AC97_I2S                        1#define GPIO_MUX_LOW_27                                 27:27#define GPIO_MUX_LOW_27_GPIO                            0#define GPIO_MUX_LOW_27_AC97_I2S                        1#define GPIO_MUX_LOW_26                                 26:26#define GPIO_MUX_LOW_26_GPIO                            0#define GPIO_MUX_LOW_26_AC97_I2S                        1#define GPIO_MUX_LOW_25                                 25:25#define GPIO_MUX_LOW_25_GPIO                            0#define GPIO_MUX_LOW_25_AC97_I2S                        1#define GPIO_MUX_LOW_24                                 24:24#define GPIO_MUX_LOW_24_GPIO                            0#define GPIO_MUX_LOW_24_AC97                            1#define GPIO_MUX_LOW_23                                 23:23#define GPIO_MUX_LOW_23_GPIO                            0#define GPIO_MUX_LOW_23_ZVPORT                          1#define GPIO_MUX_LOW_22                                 22:22#define GPIO_MUX_LOW_22_GPIO                            0#define GPIO_MUX_LOW_22_ZVPORT                          1#define GPIO_MUX_LOW_21                                 21:21#define GPIO_MUX_LOW_21_GPIO                            0#define GPIO_MUX_LOW_21_ZVPORT                          1#define GPIO_MUX_LOW_20                                 20:20#define GPIO_MUX_LOW_20_GPIO                            0#define GPIO_MUX_LOW_20_ZVPORT                          1#define GPIO_MUX_LOW_19                                 19:19#define GPIO_MUX_LOW_19_GPIO                            0#define GPIO_MUX_LOW_19_ZVPORT                          1#define GPIO_MUX_LOW_18                                 18:18#define GPIO_MUX_LOW_18_GPIO                            0#define GPIO_MUX_LOW_18_ZVPORT                          1#define GPIO_MUX_LOW_17                                 17:17#define GPIO_MUX_LOW_17_GPIO                            0#define GPIO_MUX_LOW_17_ZVPORT                          1#define GPIO_MUX_LOW_16                                 16:16#define GPIO_MUX_LOW_16_GPIO                            0#define GPIO_MUX_LOW_16_ZVPORT                          1#define GPIO_MUX_LOW_15                                 15:15