#define INT_MASK_I2C_DISABLE                            0#define INT_MASK_I2C_ENABLE                             1#define INT_MASK_PWM                                    22:22#define INT_MASK_PWM_DISABLE                            0#define INT_MASK_PWM_ENABLE                             1#define INT_MASK_DMA                                    20:20#define INT_MASK_DMA_DISABLE                            0#define INT_MASK_DMA_ENABLE                             1#define INT_MASK_PCI                                    19:19#define INT_MASK_PCI_DISABLE                            0#define INT_MASK_PCI_ENABLE                             1#define INT_MASK_I2S                                    18:18#define INT_MASK_I2S_DISABLE                            0#define INT_MASK_I2S_ENABLE                             1#define INT_MASK_AC97                                   17:17#define INT_MASK_AC97_DISABLE                           0#define INT_MASK_AC97_ENABLE                            1#define INT_MASK_USB_SLAVE                              16:16#define INT_MASK_USB_SLAVE_DISABLE                      0#define INT_MASK_USB_SLAVE_ENABLE                       1#define INT_MASK_UART1                                  13:13#define INT_MASK_UART1_DISABLE                          0#define INT_MASK_UART1_ENABLE                           1#define INT_MASK_UART0                                  12:12#define INT_MASK_UART0_DISABLE                          0#define INT_MASK_UART0_ENABLE                           1#define INT_MASK_CRT_VSYNC                              11:11#define INT_MASK_CRT_VSYNC_DISABLE                      0#define INT_MASK_CRT_VSYNC_ENABLE                       1#define INT_MASK_8051                                   10:10#define INT_MASK_8051_DISABLE                           0#define INT_MASK_8051_ENABLE                            1#define INT_MASK_SSP1                                   9:9#define INT_MASK_SSP1_DISABLE                           0#define INT_MASK_SSP1_ENABLE                            1#define INT_MASK_SSP0                                   8:8#define INT_MASK_SSP0_DISABLE                           0#define INT_MASK_SSP0_ENABLE                            1#define INT_MASK_USB_HOST                               6:6#define INT_MASK_USB_HOST_DISABLE                       0#define INT_MASK_USB_HOST_ENABLE                        1#define INT_MASK_2D                                     3:3#define INT_MASK_2D_DISABLE                             0#define INT_MASK_2D_ENABLE                              1#define INT_MASK_ZVPORT                                 2:2#define INT_MASK_ZVPORT_DISABLE                         0#define INT_MASK_ZVPORT_ENABLE                          1#define INT_MASK_PANEL_VSYNC                            1:1#define INT_MASK_PANEL_VSYNC_DISABLE                    0#define INT_MASK_PANEL_VSYNC_ENABLE                     1#define INT_MASK_CMD_INTPR                              0:0#define INT_MASK_CMD_INTPR_DISABLE                      0#define INT_MASK_CMD_INTPR_ENABLE                       1#define DEBUG_CTRL                                      0x000034#define DEBUG_CTRL_MODULE                               7:5#define DEBUG_CTRL_PARTITION                            4:0#define DEBUG_CTRL_PARTITION_HIF                        0#define DEBUG_CTRL_PARTITION_CPUMEM                     1#define DEBUG_CTRL_PARTITION_PCI                        2#define DEBUG_CTRL_PARTITION_CMD_INTPR                  3#define DEBUG_CTRL_PARTITION_DISPLAY                    4#define DEBUG_CTRL_PARTITION_ZVPORT                     5#define DEBUG_CTRL_PARTITION_2D                         6#define DEBUG_CTRL_PARTITION_MIF                        8#define DEBUG_CTRL_PARTITION_USB_HOST                   10#define DEBUG_CTRL_PARTITION_SSP0                       12#define DEBUG_CTRL_PARTITION_SSP1                       13#define DEBUG_CTRL_PARTITION_UART0                      19#define DEBUG_CTRL_PARTITION_UART1                      20#define DEBUG_CTRL_PARTITION_I2C                        21#define DEBUG_CTRL_PARTITION_8051                       23#define DEBUG_CTRL_PARTITION_AC97                       24#define DEBUG_CTRL_PARTITION_I2S                        25#define DEBUG_CTRL_PARTITION_INTMEM                     26#define DEBUG_CTRL_PARTITION_DMA                        27#define DEBUG_CTRL_PARTITION_SIMULATION                 28#define CURRENT_POWER_GATE                              0x000038#define CURRENT_POWER_GATE_AC97_I2S                     18:18#define CURRENT_POWER_GATE_AC97_I2S_DISABLE             0#define CURRENT_POWER_GATE_AC97_I2S_ENABLE              1#define CURRENT_POWER_GATE_8051                         17:17#define CURRENT_POWER_GATE_8051_DISABLE                 0#define CURRENT_POWER_GATE_8051_ENABLE                  1#define CURRENT_POWER_GATE_PLL                          16:16#define CURRENT_POWER_GATE_PLL_DISABLE                  0#define CURRENT_POWER_GATE_PLL_ENABLE                   1#define CURRENT_POWER_GATE_OSCILLATOR                   15:15#define CURRENT_POWER_GATE_OSCILLATOR_DISABLE           0#define CURRENT_POWER_GATE_OSCILLATOR_ENABLE            1#define CURRENT_POWER_GATE_PLL_RECOVERY                 14:13#define CURRENT_POWER_GATE_PLL_RECOVERY_32              0#define CURRENT_POWER_GATE_PLL_RECOVERY_64              1#define CURRENT_POWER_GATE_PLL_RECOVERY_96              2#define CURRENT_POWER_GATE_PLL_RECOVERY_128             3#define CURRENT_POWER_GATE_USB_SLAVE                    12:12#define CURRENT_POWER_GATE_USB_SLAVE_DISABLE            0#define CURRENT_POWER_GATE_USB_SLAVE_ENABLE             1#define CURRENT_POWER_GATE_USB_HOST                     11:11#define CURRENT_POWER_GATE_USB_HOST_DISABLE             0#define CURRENT_POWER_GATE_USB_HOST_ENABLE              1#define CURRENT_POWER_GATE_SSP0_SSP1                    10:10#define CURRENT_POWER_GATE_SSP0_SSP1_DISABLE            0#define CURRENT_POWER_GATE_SSP0_SSP1_ENABLE             1#define CURRENT_POWER_GATE_UART1                        8:8#define CURRENT_POWER_GATE_UART1_DISABLE                0#define CURRENT_POWER_GATE_UART1_ENABLE                 1#define CURRENT_POWER_GATE_UART0                        7:7#define CURRENT_POWER_GATE_UART0_DISABLE                0#define CURRENT_POWER_GATE_UART0_ENABLE                 1#define CURRENT_POWER_GATE_GPIO_PWM_I2C                 6:6#define CURRENT_POWER_GATE_GPIO_PWM_I2C_DISABLE         0#define CURRENT_POWER_GATE_GPIO_PWM_I2C_ENABLE          1#define CURRENT_POWER_GATE_ZVPORT                       5:5#define CURRENT_POWER_GATE_ZVPORT_DISABLE               0#define CURRENT_POWER_GATE_ZVPORT_ENABLE                1#define CURRENT_POWER_GATE_CSC                          4:4#define CURRENT_POWER_GATE_CSC_DISABLE                  0#define CURRENT_POWER_GATE_CSC_ENABLE                   1#define CURRENT_POWER_GATE_2D                           3:3#define CURRENT_POWER_GATE_2D_DISABLE                   0#define CURRENT_POWER_GATE_2D_ENABLE                    1#define CURRENT_POWER_GATE_DISPLAY                      2:2#define CURRENT_POWER_GATE_DISPLAY_DISABLE              0#define CURRENT_POWER_GATE_DISPLAY_ENABLE               1#define CURRENT_POWER_GATE_INTMEM                       1:1#define CURRENT_POWER_GATE_INTMEM_DISABLE               0#define CURRENT_POWER_GATE_INTMEM_ENABLE                1#define CURRENT_POWER_GATE_HOST                         0:0#define CURRENT_POWER_GATE_HOST_DISABLE                 0#define CURRENT_POWER_GATE_HOST_ENABLE                  1#define CURRENT_POWER_CLOCK                             0x00003C#define CURRENT_POWER_CLOCK_P2XCLK_SELECT               29:29#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_288           0#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_336           1#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER              28:27#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_1            0#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_3            1#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_5            2#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT                26:24#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_0              0#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_1              1#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_2              2#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_3              3#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_4              4#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_5              5#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_6              6#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_7              7#define CURRENT_POWER_CLOCK_V2XCLK_SELECT               20:20#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_288           0#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_336           1#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER              19:19#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_1            0#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_3            1#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT                18:16#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_0              0#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_1              1#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_2              2#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_3              3#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_4              4#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_5              5#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_6              6#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_7              7#define CURRENT_POWER_CLOCK_MCLK_SELECT                 12:12#define CURRENT_POWER_CLOCK_MCLK_SELECT_288             0#define CURRENT_POWER_CLOCK_MCLK_SELECT_336             1#define CURRENT_POWER_CLOCK_MCLK_DIVIDER                11:11#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_1              0#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_3              1#define CURRENT_POWER_CLOCK_MCLK_SHIFT                  10:8#define CURRENT_POWER_CLOCK_MCLK_SHIFT_0                0#define CURRENT_POWER_CLOCK_MCLK_SHIFT_1                1#define CURRENT_POWER_CLOCK_MCLK_SHIFT_2                2#define CURRENT_POWER_CLOCK_MCLK_SHIFT_3                3#define CURRENT_POWER_CLOCK_MCLK_SHIFT_4                4#define CURRENT_POWER_CLOCK_MCLK_SHIFT_5                5#define CURRENT_POWER_CLOCK_MCLK_SHIFT_6                6#define CURRENT_POWER_CLOCK_MCLK_SHIFT_7                7#define CURRENT_POWER_CLOCK_M2XCLK_SELECT               4:4#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_288           0#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_336           1#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER              3:3#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_1            0#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_3            1#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT                2:0#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_0              0#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_1              1#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_2              2#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_3              3#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_4              4#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_5              5#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_6              6#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_7              7#define POWER_MODE0_GATE                                0x000040#define POWER_MODE0_GATE_AC97_I2S                       18:18#define POWER_MODE0_GATE_AC97_I2S_DISABLE               0#define POWER_MODE0_GATE_AC97_I2S_ENABLE                1#define POWER_MODE0_GATE_8051                           17:17#define POWER_MODE0_GATE_8051_DISABLE                   0#define POWER_MODE0_GATE_8051_ENABLE                    1#define POWER_MODE0_GATE_USB_SLAVE                      12:12#define POWER_MODE0_GATE_USB_SLAVE_DISABLE              0#define POWER_MODE0_GATE_USB_SLAVE_ENABLE               1#define POWER_MODE0_GATE_USB_HOST                       11:11#define POWER_MODE0_GATE_USB_HOST_DISABLE               0#define POWER_MODE0_GATE_USB_HOST_ENABLE                1#define POWER_MODE0_GATE_SSP0_SSP1                      10:10#define POWER_MODE0_GATE_SSP0_SSP1_DISABLE              0#define POWER_MODE0_GATE_SSP0_SSP1_ENABLE               1#define POWER_MODE0_GATE_UART1                          8:8#define POWER_MODE0_GATE_UART1_DISABLE                  0#define POWER_MODE0_GATE_UART1_ENABLE                   1#define POWER_MODE0_GATE_UART0                          7:7#define POWER_MODE0_GATE_UART0_DISABLE                  0#define POWER_MODE0_GATE_UART0_ENABLE                   1#define POWER_MODE0_GATE_GPIO_PWM_I2C                   6:6#define POWER_MODE0_GATE_GPIO_PWM_I2C_DISABLE           0#define POWER_MODE0_GATE_GPIO_PWM_I2C_ENABLE            1#define POWER_MODE0_GATE_ZVPORT                         5:5#define POWER_MODE0_GATE_ZVPORT_DISABLE                 0#define POWER_MODE0_GATE_ZVPORT_ENABLE                  1#define POWER_MODE0_GATE_CSC                            4:4#define POWER_MODE0_GATE_CSC_DISABLE                    0#define POWER_MODE0_GATE_CSC_ENABLE                     1#define POWER_MODE0_GATE_2D                             3:3#define POWER_MODE0_GATE_2D_DISABLE                     0#define POWER_MODE0_GATE_2D_ENABLE                      1#define POWER_MODE0_GATE_DISPLAY                        2:2#define POWER_MODE0_GATE_DISPLAY_DISABLE                0#define POWER_MODE0_GATE_DISPLAY_ENABLE                 1