?? 2410init.s
字號:
# mov pc,lr @ The LR register won't be valid if the current mode is not SVC mode.
# Setup IRQ handler
ldr r0,=HandleIRQ @ This routine is needed
ldr r1,=IsrIRQ @ if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
str r1,[r0]
# Copy and paste RW data/zero initialized data
ldr r0, = Image_RO_Limit@ Get pointer to ROM data
ldr r1, = Image_RW_Base @ and RAM copy
ldr r3, = Image_ZI_Base
# Zero init base => top of initialised data
cmp r0, r1 @ Check that they are different
beq F2
F1:
cmp r1, r3 @ Copy init data
ldrcc r2, [r0], #4 @ --> LDRCC r2, [r0] + ADD r0, r0, #4
strcc r2, [r1], #4 @ --> STRCC r2, [r1] + ADD r1, r1, #4
bcc F1
F2:
ldr r1, = Image_ZI_Limit@ Top of zero init segment
mov r2, #0
B5:
cmp r3, r1 @ Zero init
strcc r2, [r3], #4
bcc B5
MRS r0, CPSR
BIC r0, r0, #0x80 @ IRQ enable
MSR CPSR_cxsf, r0
/* jump to Main() */
.ifdef THUMBCODE @ for start-up code for Thumb mode
orr lr,pc,#1
bx lr
.thumb
bl Main @ Don't use main() because...
.else
.arm
bl Main @ Don't use main() because...
.endif
b .
/*
#ifdef CONFIG_S3C2410_NAND_BOOT
@
@ copy_myself: copy to ram
@
copy_myself:
mov r10, lr
@ reset NAND
ldr r1, =NFCONF
ldr r2, =0xf830 @ initial value
str r2, [r1, #0x00]
ldr r2, [r1, #0x00]
bic r2, r2, #0x800 @ enable chip
str r2, [r1, #0x00]
mov r2, #0xff @ RESET command
strb r2, [r1, #0x04]
mov r3, #0 @ wait
1: add r3, r3, #0x1
cmp r3, #0xa
blt 1b
2: ldr r2, [r1, #0x10] @ wait ready
tst r2, #0x1
beq 2b
ldr r2, [r1, #0x00]
orr r2, r2, #0x800 @ disable chip
str r2, [r1, #0x00]
@ get read to call C functions (for nand_read())
ldr sp, =0x32000000 @DW_STACK_START @ setup stack pointer
mov fp, #0 @ no previous frame, so fp=0
@ copy to RAM
ldr r0, =0x30000000
mov r1, #0x0
mov r2, #0x20000
bl nand_read_ll
tst r0, #0x0
beq ok_nand_read
#ifdef CONFIG_DEBUG
bad_nand_read:
ldr r0, STR_FAIL
ldr r1, SerBase
bl PrintWord
1: b 1b @ infinite loop
#endif
ok_nand_read:
#ifdef CONFIG_DEBUG
ldr r0, STR_OK
ldr r1, SerBase
bl PrintWord
#endif
@ verify
mov r0, #0
ldr r1, =0x33f00000
mov r2, #0x400 @ 4 bytes * 1024 = 4K-bytes
go_next:
ldr r3, [r0], #4
ldr r4, [r1], #4
teq r3, r4
bne notmatch
subs r2, r2, #4
beq done_nand_read
bne go_next
notmatch:
#ifdef CONFIG_DEBUG
sub r0, r0, #4
ldr r1, SerBase
bl PrintHexWord
ldr r0, STR_FAIL
ldr r1, SerBase
bl PrintWord
#endif
1: b 1b
done_nand_read:
#ifdef CONFIG_DEBUG
ldr r0, STR_OK
ldr r1, SerBase
bl PrintWord
#endif
mov pc, r10
@ clear memory
@ r0: start address
@ r1: length
mem_clear:
mov r2, #0
mov r3, r2
mov r4, r2
mov r5, r2
mov r6, r2
mov r7, r2
mov r8, r2
mov r9, r2
clear_loop:
stmia r0!, {r2-r9}
subs r1, r1, #(8 * 4)
bne clear_loop
mov pc, lr
#endif @ CONFIG_S3C2410_NAND_BOOT
#ifdef CONFIG_DEBUG
@ PrintHexNibble : prints the least-significant nibble in R0 as a
@ hex digit
@ r0 contains nibble to write as Hex
@ r1 contains base of serial port
@ writes ro with XXX, modifies r0,r1,r2
@ TODO : write ro with XXX reg to error handling
@ Falls through to PrintChar
PrintHexNibble:
adr r2, HEX_TO_ASCII_TABLE
and r0, r0, #0xF
ldr r0, [r2, r0] @ convert to ascii
b PrintChar
@ PrintChar : prints the character in R0
@ r0 contains the character
@ r1 contains base of serial port
@ writes ro with XXX, modifies r0,r1,r2
@ TODO : write ro with XXX reg to error handling
PrintChar:
TXBusy:
ldr r2, [r1, #0x10]
and r2, r2, #4
tst r2, #4
beq TXBusy
str r0, [r1, #0x20]
mov pc, lr
@ PrintWord : prints the 4 characters in R0
@ r0 contains the binary word
@ r1 contains the base of the serial port
@ writes ro with XXX, modifies r0,r1,r2
@ TODO : write ro with XXX reg to error handling
PrintWord:
mov r3, r0
mov r4, lr
bl PrintChar
mov r0, r3, LSR #8 @ shift word right 8 bits
bl PrintChar
mov r0, r3, LSR #16 @ shift word right 16 bits
bl PrintChar
mov r0, r3, LSR #24 @ shift word right 24 bits
bl PrintChar
mov r0, #'\r'
bl PrintChar
mov r0, #'\n'
bl PrintChar
mov pc, r4
@ PrintHexWord : prints the 4 bytes in R0 as 8 hex ascii characters
@ followed by a newline
@ r0 contains the binary word
@ r1 contains the base of the serial port
@ writes ro with XXX, modifies r0,r1,r2
@ TODO : write ro with XXX reg to error handling
PrintHexWord:
mov r4, lr
mov r3, r0
mov r0, r3, LSR #28
bl PrintHexNibble
mov r0, r3, LSR #24
bl PrintHexNibble
mov r0, r3, LSR #20
bl PrintHexNibble
mov r0, r3, LSR #16
bl PrintHexNibble
mov r0, r3, LSR #12
bl PrintHexNibble
mov r0, r3, LSR #8
bl PrintHexNibble
mov r0, r3, LSR #4
bl PrintHexNibble
mov r0, r3
bl PrintHexNibble
mov r0, #'\r'
bl PrintChar
mov r0, #'\n'
bl PrintChar
mov pc, r4
.align 2
HEX_TO_ASCII_TABLE:
.ascii "0123456789ABCDEF"
STR_STACK:
.ascii "STKP"
STR_UNDEF:
.ascii "UNDF"
STR_SWI:
.ascii "SWI "
STR_PREFETCH_ABORT:
.ascii "PABT"
STR_DATA_ABORT:
.ascii "DABT"
STR_IRQ:
.ascii "IRQ "
STR_FIQ:
.ascii "FIQ"
STR_NOT_USED:
.ascii "NUSD"
.align 2
STR_OK:
.ascii "OK "
STR_FAIL:
.ascii "FAIL"
STR_CR:
.ascii "\r\n"
#endif
.align 4
SerBase:
#if defined(CONFIG_SERIAL_UART0)
.long ULCON0
#elif defined(CONFIG_SERIAL_UART1)
.long ULCON1
#elif defined(CONFIG_SERIAL_UART2)
.long ULCON2
#else
#error not defined base address of serial
#endif
*/
#=============================================================================================
#SMRDATA
# Memory configuration should be optimized for best performance
# The following parameter is not optimized.
# Memory access cycle parameter strategy
# 1) The memory settings is safe parameters even at HCLK=75Mhz.
# 2) SDRAM refresh period is for HCLK=75Mhz.
#=============================================================================================
.ltorg
SMRDATA:
.long (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
.long ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) @ GCS0
.long ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) @ GCS1
.long ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) @ GCS2
.long ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) @ GCS3
.long ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) @ GCS4
.long ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) @ GCS5
.long ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) @ GCS6
.long ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) @ GCS7
.long ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
.long 0x32 @ SCLK power saving mode, BANKSIZE 128M/128M
.long 0x30 @ MRSR6 CL=3clk
.long 0x30 @ MRSR7
# .long 0x20 @ MRSR6 CL=2clk
# .long 0x20 @ MRSR7
#=======================================================================================================================
# ARM core's exception and user interrupt handler store address
# The address may be different between the different assemble after link.
#=============================================================================================
.align
.equ HandleReset, _ISR_STARTADDRESS
.equ HandleUndef, _ISR_STARTADDRESS+4
.equ HandleSWI, _ISR_STARTADDRESS+4*2
.equ HandlePabort, _ISR_STARTADDRESS+4*3
.equ HandleDabort, _ISR_STARTADDRESS+4*4
.equ HandleReserved, _ISR_STARTADDRESS+4*5
.equ HandleIRQ, _ISR_STARTADDRESS+4*6
.equ HandleFIQ, _ISR_STARTADDRESS+4*7
#Don't use the label 'IntVectorTable',
#The value of IntVectorTable is different with the address you think it may be.
#IntVectorTable
.equ HandleEINT0, _ISR_STARTADDRESS+4*8
.equ HandleEINT1, _ISR_STARTADDRESS+4*9
.equ HandleEINT2, _ISR_STARTADDRESS+4*10
.equ HandleEINT3, _ISR_STARTADDRESS+4*11
.equ HandleEINT4_7, _ISR_STARTADDRESS+4*12
.equ HandleEINT8_23, _ISR_STARTADDRESS+4*13
.equ HandleRSV6, _ISR_STARTADDRESS+4*14
.equ HandleBATFLT, _ISR_STARTADDRESS+4*15
.equ HandleTICK, _ISR_STARTADDRESS+4*16
.equ HandleWDT, _ISR_STARTADDRESS+4*17
.equ HandleTIMER0, _ISR_STARTADDRESS+4*18
.equ HandleTIMER1, _ISR_STARTADDRESS+4*19
.equ HandleTIMER2, _ISR_STARTADDRESS+4*20
.equ HandleTIMER3, _ISR_STARTADDRESS+4*21
.equ HandleTIMER4, _ISR_STARTADDRESS+4*22
.equ HandleUART2, _ISR_STARTADDRESS+4*23
.equ HandleLCD, _ISR_STARTADDRESS+4*24
.equ HandleDMA0, _ISR_STARTADDRESS+4*25
.equ HandleDMA1, _ISR_STARTADDRESS+4*26
.equ HandleDMA2, _ISR_STARTADDRESS+4*27
.equ HandleDMA3, _ISR_STARTADDRESS+4*28
.equ HandleMMC, _ISR_STARTADDRESS+4*29
.equ HandleSPI0, _ISR_STARTADDRESS+4*30
.equ HandleUART1, _ISR_STARTADDRESS+4*31
.equ HandleRSV24, _ISR_STARTADDRESS+4*32
.equ HandleUSBD, _ISR_STARTADDRESS+4*33
.equ HandleUSBH, _ISR_STARTADDRESS+4*34
.equ HandleIIC, _ISR_STARTADDRESS+4*35
.equ HandleUART, _ISR_STARTADDRESS+4*36
.equ HandleSPI1, _ISR_STARTADDRESS+4*37
.equ HandleRTC, _ISR_STARTADDRESS+4*38
.equ HandleADC, _ISR_STARTADDRESS+4*39
.end
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