?? s3c2410a.s
字號:
;// <o1.14..15> PB7 <0=> Input <1=> Output <2=> nXDACK1 <3=> Reserved
;// <o1.16..17> PB8 <0=> Input <1=> Output <2=> nXDREQ1 <3=> Reserved
;// <o1.18..19> PB9 <0=> Input <1=> Output <2=> nXDACK0 <3=> Reserved
;// <o1.20..21> PB10 <0=> Input <1=> Output <2=> nXDREQ0 <3=> Reserved
;// <h> Pull-up Resistors
;// <o2.0> PB0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PB1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PB2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PB3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PB4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PB5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PB6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PB7 Pull-up <0=> Enabled <1=> Disabled
;// <o2.8> PB8 Pull-up <0=> Enabled <1=> Disabled
;// <o2.9> PB9 Pull-up <0=> Enabled <1=> Disabled
;// <o2.10> PB10 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOB_SETUP EQU 1
PCONB_Val EQU 0x00000FFF
PUPB_Val EQU 0x00000000
;// <e> Port C
;// <o1.0..1> PC0 <0=> Input <1=> Output <2=> LEND <3=> Reserved
;// <o1.2..3> PC1 <0=> Input <1=> Output <2=> VCLK <3=> Reserved
;// <o1.4..5> PC2 <0=> Input <1=> Output <2=> VLINE <3=> Reserved
;// <o1.6..7> PC3 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved
;// <o1.8..9> PC4 <0=> Input <1=> Output <2=> VM <3=> Reserved
;// <o1.10..11> PC5 <0=> Input <1=> Output <2=> LCDVF2 <3=> Reserved
;// <o1.12..13> PC6 <0=> Input <1=> Output <2=> LCDVF1 <3=> Reserved
;// <o1.14..15> PC7 <0=> Input <1=> Output <2=> LCDVF0 <3=> Reserved
;// <o1.16..17> PC8 <0=> Input <1=> Output <2=> VD[0] <3=> Reserved
;// <o1.18..19> PC9 <0=> Input <1=> Output <2=> VD[1] <3=> Reserved
;// <o1.20..21> PC10 <0=> Input <1=> Output <2=> VD[2] <3=> Reserved
;// <o1.22..23> PC11 <0=> Input <1=> Output <2=> VD[3] <3=> Reserved
;// <o1.24..25> PC12 <0=> Input <1=> Output <2=> VD[4] <3=> Reserved
;// <o1.26..27> PC13 <0=> Input <1=> Output <2=> VD[5] <3=> Reserved
;// <o1.28..29> PC14 <0=> Input <1=> Output <2=> VD[6] <3=> Reserved
;// <o1.30..31> PC15 <0=> Input <1=> Output <2=> VD[7] <3=> Reserved
;// <h> Pull-up Resistors
;// <o2.0> PC0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PC1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PC2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PC3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PC4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PC5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PC6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PC7 Pull-up <0=> Enabled <1=> Disabled
;// <o2.8> PC8 Pull-up <0=> Enabled <1=> Disabled
;// <o2.9> PC9 Pull-up <0=> Enabled <1=> Disabled
;// <o2.10> PC10 Pull-up <0=> Enabled <1=> Disabled
;// <o2.11> PC11 Pull-up <0=> Enabled <1=> Disabled
;// <o2.12> PC12 Pull-up <0=> Enabled <1=> Disabled
;// <o2.13> PC13 Pull-up <0=> Enabled <1=> Disabled
;// <o2.14> PC14 Pull-up <0=> Enabled <1=> Disabled
;// <o2.15> PC15 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOC_SETUP EQU 0
PCONC_Val EQU 0xAAAAAAAA
PUPC_Val EQU 0x00000000
;// <e> Port D
;// <o1.0..1> PD0 <0=> Input <1=> Output <2=> VD[8] <3=> Reserved
;// <o1.2..3> PD1 <0=> Input <1=> Output <2=> VD[9] <3=> Reserved
;// <o1.4..5> PD2 <0=> Input <1=> Output <2=> VD[10] <3=> Reserved
;// <o1.6..7> PD3 <0=> Input <1=> Output <2=> VD[11] <3=> Reserved
;// <o1.8..9> PD4 <0=> Input <1=> Output <2=> VD[12] <3=> Reserved
;// <o1.10..11> PD5 <0=> Input <1=> Output <2=> VD[13] <3=> Reserved
;// <o1.12..13> PD6 <0=> Input <1=> Output <2=> VD[14] <3=> Reserved
;// <o1.14..15> PD7 <0=> Input <1=> Output <2=> VD[15] <3=> Reserved
;// <o1.16..17> PD8 <0=> Input <1=> Output <2=> VD[16] <3=> Reserved
;// <o1.18..19> PD9 <0=> Input <1=> Output <2=> VD[17] <3=> Reserved
;// <o1.20..21> PD10 <0=> Input <1=> Output <2=> VD[18] <3=> Reserved
;// <o1.22..23> PD11 <0=> Input <1=> Output <2=> VD[19] <3=> Reserved
;// <o1.24..25> PD12 <0=> Input <1=> Output <2=> VD[20] <3=> Reserved
;// <o1.26..27> PD13 <0=> Input <1=> Output <2=> VD[21] <3=> Reserved
;// <o1.28..29> PD14 <0=> Input <1=> Output <2=> VD[22] <3=> nSS1
;// <o1.30..31> PD15 <0=> Input <1=> Output <2=> VD[23] <3=> nSS0
;// <h> Pull-up Resistors
;// <o2.0> PD0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PD1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PD2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PD3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PD4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PD5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PD6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PD7 Pull-up <0=> Enabled <1=> Disabled
;// <o2.8> PD8 Pull-up <0=> Enabled <1=> Disabled
;// <o2.9> PD9 Pull-up <0=> Enabled <1=> Disabled
;// <o2.10> PD10 Pull-up <0=> Enabled <1=> Disabled
;// <o2.11> PD11 Pull-up <0=> Enabled <1=> Disabled
;// <o2.12> PD12 Pull-up <0=> Enabled <1=> Disabled
;// <o2.13> PD13 Pull-up <0=> Enabled <1=> Disabled
;// <o2.14> PD14 Pull-up <0=> Enabled <1=> Disabled
;// <o2.15> PD15 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOD_SETUP EQU 0
PCOND_Val EQU 0x00000000
PUPD_Val EQU 0x00000000
;// <e> Port E
;// <o1.0..1> PE0 <0=> Input <1=> Output <2=> I2SLRCK <3=> Reserved
;// <o1.2..3> PE1 <0=> Input <1=> Output <2=> I2SSCLK <3=> Reserved
;// <o1.4..5> PE2 <0=> Input <1=> Output <2=> CDCLK <3=> Reserved
;// <o1.6..7> PE3 <0=> Input <1=> Output <2=> I2SDI <3=> nSS0
;// <o1.8..9> PE4 <0=> Input <1=> Output <2=> I2SDO <3=> I2SSDI
;// <o1.10..11> PE5 <0=> Input <1=> Output <2=> SDCLK <3=> Reserved
;// <o1.12..13> PE6 <0=> Input <1=> Output <2=> SDCMD <3=> Reserved
;// <o1.14..15> PE7 <0=> Input <1=> Output <2=> SDDAT0 <3=> Reserved
;// <o1.16..17> PE8 <0=> Input <1=> Output <2=> SDDAT1 <3=> Reserved
;// <o1.18..19> PE9 <0=> Input <1=> Output <2=> SDDAT2 <3=> Reserved
;// <o1.20..21> PE10 <0=> Input <1=> Output <2=> SDDAT3 <3=> Reserved
;// <o1.22..23> PE11 <0=> Input <1=> Output <2=> SPIMISO0 <3=> Reserved
;// <o1.24..25> PE12 <0=> Input <1=> Output <2=> SPIMOSI0 <3=> Reserved
;// <o1.26..27> PE13 <0=> Input <1=> Output <2=> SPICLK0 <3=> Reserved
;// <o1.28..29> PE14 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved
;// <o1.30..31> PE15 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved
;// <h> Pull-up Resistors
;// <o2.0> PE0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PE1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PE2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PE3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PE4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PE5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PE6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PE7 Pull-up <0=> Enabled <1=> Disabled
;// <o2.8> PE8 Pull-up <0=> Enabled <1=> Disabled
;// <o2.9> PE9 Pull-up <0=> Enabled <1=> Disabled
;// <o2.10> PE10 Pull-up <0=> Enabled <1=> Disabled
;// <o2.11> PE11 Pull-up <0=> Enabled <1=> Disabled
;// <o2.12> PE12 Pull-up <0=> Enabled <1=> Disabled
;// <o2.13> PE13 Pull-up <0=> Enabled <1=> Disabled
;// <o2.14> PE14 Pull-up <0=> Enabled <1=> Disabled
;// <o2.15> PE15 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOE_SETUP EQU 0
PCONE_Val EQU 0x00000000
PUPE_Val EQU 0x00000000
;// <e> Port F
;// <o1.0..1> PF0 <0=> Input <1=> Output <2=> EINT[0] <3=> Reserved
;// <o1.2..3> PF1 <0=> Input <1=> Output <2=> EINT[1] <3=> Reserved
;// <o1.4..5> PF2 <0=> Input <1=> Output <2=> EINT[2] <3=> Reserved
;// <o1.6..7> PF3 <0=> Input <1=> Output <2=> EINT[3] <3=> Reserved
;// <o1.8..9> PF4 <0=> Input <1=> Output <2=> EINT[4] <3=> Reserved
;// <o1.10..11> PF5 <0=> Input <1=> Output <2=> EINT[5] <3=> Reserved
;// <o1.12..13> PF6 <0=> Input <1=> Output <2=> EINT[6] <3=> Reserved
;// <o1.14..15> PF7 <0=> Input <1=> Output <2=> EINT[7] <3=> Reserved
;// <h> Pull-up Resistors
;// <o2.0> PF0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PF1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PF2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PF3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PF4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PF5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PF6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PF7 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOF_SETUP EQU 1
PCONF_Val EQU 0x000055aa
PUPF_Val EQU 0x000000ff
;// <e> Port G
;// <o1.0..1> PG0 <0=> Input <1=> Output <2=> EINT[8] <3=> Reserved
;// <o1.2..3> PG1 <0=> Input <1=> Output <2=> EINT[9] <3=> Reserved
;// <o1.4..5> PG2 <0=> Input <1=> Output <2=> EINT[10] <3=> nSS0
;// <o1.6..7> PG3 <0=> Input <1=> Output <2=> EINT[11] <3=> nSS1
;// <o1.8..9> PG4 <0=> Input <1=> Output <2=> EINT[12] <3=> LCD_PWRDN
;// <o1.10..11> PG5 <0=> Input <1=> Output <2=> EINT[13] <3=> SPIMISO1
;// <o1.12..13> PG6 <0=> Input <1=> Output <2=> EINT[14] <3=> SPIMOSI1
;// <o1.14..15> PG7 <0=> Input <1=> Output <2=> EINT[15] <3=> SPICLK1
;// <o1.16..17> PG8 <0=> Input <1=> Output <2=> EINT[16] <3=> Reserved
;// <o1.18..19> PG9 <0=> Input <1=> Output <2=> EINT[17] <3=> Reserved
;// <o1.20..21> PG10 <0=> Input <1=> Output <2=> EINT[18] <3=> Reserved
;// <o1.22..23> PG11 <0=> Input <1=> Output <2=> EINT[19] <3=> TCLK1
;// <o1.24..25> PG12 <0=> Input <1=> Output <2=> EINT[20] <3=> XMON
;// <o1.26..27> PG13 <0=> Input <1=> Output <2=> EINT[21] <3=> nXPON
;// <o1.28..29> PG14 <0=> Input <1=> Output <2=> EINT[22] <3=> YMON
;// <o1.30..31> PG15 <0=> Input <1=> Output <2=> EINT[23] <3=> nYPON
;// <h> Pull-up Resistors
;// <o2.0> PG0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PG1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PG2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PG3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PG4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PG5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PG6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PG7 Pull-up <0=> Enabled <1=> Disabled
;// <o2.8> PG8 Pull-up <0=> Enabled <1=> Disabled
;// <o2.9> PG9 Pull-up <0=> Enabled <1=> Disabled
;// <o2.10> PG10 Pull-up <0=> Enabled <1=> Disabled
;// <o2.11> PG11 Pull-up <0=> Enabled <1=> Disabled
;// <o2.12> PG12 Pull-up <0=> Enabled <1=> Disabled
;// <o2.13> PG13 Pull-up <0=> Enabled <1=> Disabled
;// <o2.14> PG14 Pull-up <0=> Enabled <1=> Disabled
;// <o2.15> PG15 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOG_SETUP EQU 0
PCONG_Val EQU 0x00000000
PUPG_Val EQU 0x00000000
;// <e> Port H
;// <o1.0..1> PH0 <0=> Input <1=> Output <2=> nCTS0 <3=> Reserved
;// <o1.2..3> PH1 <0=> Input <1=> Output <2=> nRTS0 <3=> Reserved
;// <o1.4..5> PH2 <0=> Input <1=> Output <2=> TXD[0] <3=> Reserved
;// <o1.6..7> PH3 <0=> Input <1=> Output <2=> RXD[0] <3=> Reserved
;// <o1.8..9> PH4 <0=> Input <1=> Output <2=> TXD[1] <3=> Reserved
;// <o1.10..11> PH5 <0=> Input <1=> Output <2=> RXD[1] <3=> Reserved
;// <o1.12..13> PH6 <0=> Input <1=> Output <2=> TXD[2] <3=> nRTS1
;// <o1.14..15> PH7 <0=> Input <1=> Output <2=> RXD[2] <3=> nCTS1
;// <o1.16..17> PH8 <0=> Input <1=> Output <2=> UCLK <3=> Reserved
;// <o1.18..19> PH9 <0=> Input <1=> Output <2=> CLKOUT0 <3=> Reserved
;// <o1.20..21> PH10 <0=> Input <1=> Output <2=> CLKOUT1 <3=> Reserved
;// <h> Pull-up Resistors
;// <o2.0> PH0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PH1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PH2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PH3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PH4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PH5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PH6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PH7 Pull-up <0=> Enabled <1=> Disabled
;// <o2.8> PH8 Pull-up <0=> Enabled <1=> Disabled
;// <o2.9> PH9 Pull-up <0=> Enabled <1=> Disabled
;// <o2.10> PH10 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOH_SETUP EQU 0
PCONH_Val EQU 0x000007FF
PUPH_Val EQU 0x00000000
;// </e>
PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.
AREA RESET, CODE, READONLY
ARM
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
NOP ; Reserved Vector
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
IF IntVT_SETUP <> 0
;Interrupt Vector Table Address
HandleEINT0 EQU IntVTAddress
HandleEINT1 EQU IntVTAddress +4
HandleEINT2 EQU IntVTAddress +4*2
HandleEINT3 EQU IntVTAddress +4*3
HandleEINT4_7 EQU IntVTAddress +4*4
HandleEINT8_23 EQU IntVTAddress +4*5
HandleReserved EQU IntVTAddress +4*6
HandleBATFLT EQU IntVTAddress +4*7
HandleTICK EQU IntVTAddress +4*8
HandleWDT EQU IntVTAddress +4*9
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