?? s3c2410a.s
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;/*****************************************************************************/
;/* S3C2440A.S: Startup file for Samsung S3C440A */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>> */
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools. */
;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
;/* This software may only be used under the terms of a valid, current, */
;/* end user licence from KEIL for a compatible version of KEIL software */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/
; *** Startup Code (executed after Reset) ***
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
;// <h> Stack Configuration (Stack Sizes in Bytes)
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
;// </h>
UND_Stack_Size EQU 0x00000400
SVC_Stack_Size EQU 0x00001000
ABT_Stack_Size EQU 0x00000400
FIQ_Stack_Size EQU 0x00001000
IRQ_Stack_Size EQU 0x00001000
USR_Stack_Size EQU 0x00003800
Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size)
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
Stack_Top EQU Stack_Mem + Stack_Size
;// <h> Heap Configuration
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>
Heap_Size EQU 0x00004800
AREA HEAP, NOINIT, READWRITE, ALIGN=3
Heap_Mem SPACE Heap_Size
;INT CONFIG
INT_BASE EQU 0x4A000000
SRCPND_OFS EQU 0x0
INTMSK_OFS EQU 0x8
INTPND_OFS EQU 0x10
INTSUBMASK_OFS EQU 0x1c
INT_SETUP EQU 1
INTMSK_VAL EQU 0xFFFFFFFF
INTSUBMASK_VAL EQU 0X7FF
; Clock Management definitions
CLK_BASE EQU 0x4C000000 ; Clock Base Address
LOCKTIME_OFS EQU 0x00 ; LOCKTIME Offset
MPLLCON_OFS EQU 0x04 ; MPLLCON Offset
UPLLCON_OFS EQU 0X08 ; UPLLCON Offset
CLKCON_OFS EQU 0x0C ; CLKCON Offset
CLKSLOW_OFS EQU 0x10 ; CLKSLOW Offset
CLKDIVN_OFS EQU 0X14 ; CLDKIVN Offset
CAMDIVN_OFS EQU 0X18 ; CAMDIVN Offset
;// <e> Clock Management
;// <h> MPLL Settings
;// <i> Mpll = (m * Fin) / (p * 2^s)
;// <o1.12..19> MDIV: Main divider <0x0-0xFF>
;// <i> m = MDIV + 8
;// <o1.4..9> PDIV: Pre-divider <0x0-0x3F>
;// <i> p = PDIV + 2
;// <o1.0..1> SDIV: Post Divider <0x0-0x03>
;// <i> s = SDIV
;// </h>
;// <h> UPLL Settings
;// <i> Upll = ( m * Fin) / (p * 2^s),Uclk must be 48MHZ to USB device
;// <o2.12..19> MDIV: Main divider <0x1-0xF8>
;// <i> m = MDIV + 8,if Fin=12MHZ MDIV could be 0x38
;// <o2.4..9> PDIV: Pre-divider <0x1-0x3E>
;// <i> p = PDIV + 2,if Fin=12MHZ PDIV could be 0x2
;// <o2.0..1> SDIV: Post Divider <0x0-0x03>
;// <i> s = SDIV ,if Fin=12MHZ SDIV could be 0x2
;// </h>
;// <h>LOCK TIME
;// <o5.0..11> LTIME CNT: MPLL Lock Time Count <0x0-0xFFF>
;// <o5.12..23> LTIME CNT: UPLL Lock Time Count <0x0-0xFFF>
;// </h>
;// <h> Master Clock
;// <i> PLL Clock: FCLK = FMPLL
;// <i> Slow Clock: FCLK = Fin / (2 * SLOW_VAL), SLOW_VAL > 0
;// <i> Slow Clock: FCLK = Fin, SLOW_VAL = 0
;// <o4.7> UCLK_ON: UCLK ON
;// <i> 0: UCLK ON(UPLL is also turned on) 1: UCLK OFF (UPLL is also turned off)
;// <o4.5> MPLL_OFF: Turn off PLL
;// <i> 0: Turn on PLL.After PLL stabilization time (minimum 300us), SLOW_BIT can be cleared to 0. 1: Turn off PLL. PLL is turned off only when SLOW_BIT is 1.
;// <o4.4> SLOW_BIT: Slow Clock
;// <o4.0..2> SLOW_VAL: Slow Clock divider <0x0-0x7>
;// </h>
;// <h> CLOCK DIVIDER CONTROL
;// <o6.1> HDIVN
;// <i> 0: HCLK = FCLK/1, 01 : HCLK = FCLK/2
;// <o6.0> PDIVN
;// <i> 0: PCLK has the clock same as the HCLK/1,1: PCLK has the clock same as the HCLK/2
;// </h>
;// <h> Clock Generation
;// <o3.18> SPI <0=> Disable <1=> Enable
;// <o3.17> IIS <0=> Disable <1=> Enable
;// <o3.16> IIC <0=> Disable <1=> Enable
;// <o3.15> ADC <0=> Disable <1=> Enable
;// <o3.14> RTC <0=> Disable <1=> Enable
;// <o3.13> GPIO <0=> Disable <1=> Enable
;// <o3.12> UART2 <0=> Disable <1=> Enable
;// <o3.11> UART1 <0=> Disable <1=> Enable
;// <o3.10> UART0 <0=> Disable <1=> Enable
;// <o3.9> SDI <0=> Disable <1=> Enable
;// <o3.8> PWMTIMER <0=> Disable <1=> Enable
;// <o3.7> USB device <0=> Disable <1=> Enable
;// <o3.6> USB host <0=> Disable <1=> Enable
;// <o3.5> LCDC <0=> Disable <1=> Enable
;// <o3.4> NAND FLASH Controller <0=> Disable <1=> Enable
;// <o3.3> POWER-OFF <0=> Disable <1=> Enable
;// <o3.2> IDLE BIT <0=> Disable <1=> Enable
;// <O3.0> SM_BIT <0=> Disable <1=> Enable
;// </h>
;// </e>
CLK_SETUP EQU 1
MPLLCON_Val EQU 0x0005C042
UPLLCON_Val EQU 0x00028080
CLKCON_Val EQU 0x0007FFF0
CLKSLOW_Val EQU 0x00000004
LOCKTIME_Val EQU 0x00FFFFFF
CLKDIVN_Val EQU 0X00000003
;Interrupt definitions
INTOFFSET EQU 0X4A000014 ;Address of Interrupt offset Register
;//<e> Interrupt Vector Table
;// <o1.0..31> Interrupt Vector address <0x20-0x3fffff78>
;// <i> You could define Interuupt Vctor Table address.
;// <i> The Interrupt Vector Table address must be word aligned adress.
;//</e>
IntVT_SETUP EQU 1
IntVTAddress EQU 0x33FFFF20
; Watchdog Timer definitions
WT_BASE EQU 0x53000000 ; WT Base Address
WTCON_OFS EQU 0x00 ; WTCON Offset
WTDAT_OFS EQU 0x04 ; WTDAT Offset
WTCNT_OFS EQU 0x08 ; WTCNT Offset
;// <e> Watchdog Timer
;// <o1.5> Watchdog Timer Enable/Disable
;// <o1.0> Reset Enable/Disable
;// <o1.2> Interrupt Enable/Disable
;// <o1.3..4> Clock Select
;// <0=> 1/16 <1=> 1/32 <2=> 1/64 <3=> 1/128
;// <i> Clock Division Factor
;// <o1.8..15> Prescaler Value <0x0-0xFF>
;// <o2.0..15> Time-out Value <0x0-0xFFFF>
;// </e>
WT_SETUP EQU 1
WTCON_Val EQU 0x00000000
WTDAT_Val EQU 0x00008000
; Memory Controller definitions
MC_BASE EQU 0x48000000 ; Memory Controller Base Address
;// <e> Memory Controller
MC_SETUP EQU 1
;// <h> Bank 0
;// <o0.0..1> PMC: Page Mode Configuration
;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
;// <o0.2..3> Tpac: Page Mode Access Cycle
;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
;// <o0.4..5> Tcah: Address Holding Time after nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o0.6..7> Toch: Chip Select Hold on nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o0.8..10> Tacc: Access Cycle
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
;// <o0.11..12> Tcos: Chip Select Set-up nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o0.13..14> Tacs: Address Set-up before nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// </h>
;//
;// <h> Bank 1
;// <o8.4..5> DW: Data Bus Width
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
;// <o8.6> WS: WAIT Status
;// <0=> WAIT Disable
;// <1=> WAIT Enable
;// <o8.7> ST: SRAM Type
;// <0=> Not using UB/LB
;// <1=> Using UB/LB
;// <o1.0..1> PMC: Page Mode Configuration
;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
;// <o1.2..3> Tpac: Page Mode Access Cycle
;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
;// <o1.4..5> Tcah: Address Holding Time after nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o1.6..7> Toch: Chip Select Hold on nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o1.8..10> Tacc: Access Cycle
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
;// <o1.11..12> Tcos: Chip Select Set-up nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o1.13..14> Tacs: Address Set-up before nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// </h>
;//
;// <h> Bank 2
;// <o8.8..9> DW: Data Bus Width
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
;// <o8.10> WS: WAIT Status
;// <0=> WAIT Disable
;// <1=> WAIT Enable
;// <o8.11> ST: SRAM Type
;// <0=> Not using UB/LB
;// <1=> Using UB/LB
;// <o2.0..1> PMC: Page Mode Configuration
;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
;// <o2.2..3> Tpac: Page Mode Access Cycle
;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
;// <o2.4..5> Tcah: Address Holding Time after nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o2.6..7> Toch: Chip Select Hold on nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o2.8..10> Tacc: Access Cycle
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
;// <o2.11..12> Tcos: Chip Select Set-up nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o2.13..14> Tacs: Address Set-up before nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// </h>
;//
;// <h> Bank 3
;// <o8.12..13> DW: Data Bus Width
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
;// <o8.14> WS: WAIT Status
;// <0=> WAIT Disable
;// <1=> WAIT Enable
;// <o8.15> ST: SRAM Type
;// <0=> Not using UB/LB
;// <1=> Using UB/LB
;// <o3.0..1> PMC: Page Mode Configuration
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