?? dds.map.rpt
字號:
; stratixii_pll.inc ; yes ; Megafunction ; d:/altera/72/quartus/libraries/megafunctions/stratixii_pll.inc ;
; cycloneii_pll.inc ; yes ; Megafunction ; d:/altera/72/quartus/libraries/megafunctions/cycloneii_pll.inc ;
; altsyncram.tdf ; yes ; Megafunction ; d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf ;
; stratix_ram_block.inc ; yes ; Megafunction ; d:/altera/72/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc ; yes ; Megafunction ; d:/altera/72/quartus/libraries/megafunctions/lpm_mux.inc ;
; lpm_decode.inc ; yes ; Megafunction ; d:/altera/72/quartus/libraries/megafunctions/lpm_decode.inc ;
; a_rdenreg.inc ; yes ; Megafunction ; d:/altera/72/quartus/libraries/megafunctions/a_rdenreg.inc ;
; altrom.inc ; yes ; Megafunction ; d:/altera/72/quartus/libraries/megafunctions/altrom.inc ;
; altram.inc ; yes ; Megafunction ; d:/altera/72/quartus/libraries/megafunctions/altram.inc ;
; altdpram.inc ; yes ; Megafunction ; d:/altera/72/quartus/libraries/megafunctions/altdpram.inc ;
; altqpram.inc ; yes ; Megafunction ; d:/altera/72/quartus/libraries/megafunctions/altqpram.inc ;
; db/altsyncram_4m71.tdf ; yes ; Auto-Generated Megafunction ; E:/DDS/db/altsyncram_4m71.tdf ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+---------------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+---------------------------------------------+
; Estimated Total logic elements ; 30 ;
; ; ;
; Total combinational functions ; 30 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 19 ;
; -- <=2 input functions ; 11 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 11 ;
; -- arithmetic mode ; 19 ;
; ; ;
; Total registers ; 21 ;
; -- Dedicated logic registers ; 21 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 35 ;
; Total memory bits ; 10240 ;
; Total PLLs ; 1 ;
; Maximum fan-out node ; altpll0:inst1|altpll:altpll_component|_clk0 ;
; Maximum fan-out ; 32 ;
; Total fan-out ; 263 ;
; Average fan-out ; 2.71 ;
+---------------------------------------------+---------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------+--------------+
; |DDDS ; 30 (0) ; 21 (0) ; 10240 ; 0 ; 0 ; 0 ; 35 ; 0 ; |DDDS ; work ;
; |DDS:inst| ; 30 (20) ; 21 (20) ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DDDS|DDS:inst ; work ;
; |rom0:rom0_instant| ; 10 (10) ; 1 (1) ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DDDS|DDS:inst|rom0:rom0_instant ; work ;
; |altsyncram:Ram0_rtl_0| ; 0 (0) ; 0 (0) ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DDDS|DDS:inst|rom0:rom0_instant|altsyncram:Ram0_rtl_0 ; work ;
; |altsyncram_4m71:auto_generated| ; 0 (0) ; 0 (0) ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DDDS|DDS:inst|rom0:rom0_instant|altsyncram:Ram0_rtl_0|altsyncram_4m71:auto_generated ; work ;
; |altpll0:inst1| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DDDS|altpll0:inst1 ; work ;
; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DDDS|altpll0:inst1|altpll:altpll_component ; work ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-----------------------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+--------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-----------------------------+
; DDS:inst|rom0:rom0_instant|altsyncram:Ram0_rtl_0|altsyncram_4m71:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 1024 ; 10 ; -- ; -- ; 10240 ; db/rom0_rom0_3af052.hdl.mif ;
+--------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-----------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 21 ;
; Number of registers using Synchronous Clear ; 20 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 1 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------------------------+
; Registers Packed Into Inferred Megafunctions ;
+--------------------+------------------------------------+------+
; Register Name ; Megafunction ; Type ;
+--------------------+------------------------------------+------+
; DDS:inst|sinout[0] ; DDS:inst|rom0:rom0_instant|Ram0~19 ; RAM ;
; DDS:inst|sinout[1] ; DDS:inst|rom0:rom0_instant|Ram0~19 ; RAM ;
; DDS:inst|sinout[2] ; DDS:inst|rom0:rom0_instant|Ram0~19 ; RAM ;
; DDS:inst|sinout[3] ; DDS:inst|rom0:rom0_instant|Ram0~19 ; RAM ;
; DDS:inst|sinout[4] ; DDS:inst|rom0:rom0_instant|Ram0~19 ; RAM ;
; DDS:inst|sinout[5] ; DDS:inst|rom0:rom0_instant|Ram0~19 ; RAM ;
; DDS:inst|sinout[6] ; DDS:inst|rom0:rom0_instant|Ram0~19 ; RAM ;
; DDS:inst|sinout[7] ; DDS:inst|rom0:rom0_instant|Ram0~19 ; RAM ;
; DDS:inst|sinout[8] ; DDS:inst|rom0:rom0_instant|Ram0~19 ; RAM ;
; DDS:inst|sinout[9] ; DDS:inst|rom0:rom0_instant|Ram0~19 ; RAM ;
+--------------------+------------------------------------+------+
+--------------------------------------------------------------------------------------------------------+
; Source assignments for DDS:inst|rom0:rom0_instant|altsyncram:Ram0_rtl_0|altsyncram_4m71:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+------------------------------------------+
+------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: altpll0:inst1|altpll:altpll_component ;
+-------------------------------+-------------------+--------------------------------+
; Parameter Name ; Value ; Type ;
+-------------------------------+-------------------+--------------------------------+
; OPERATION_MODE ; NORMAL ; Untyped ;
; PLL_TYPE ; AUTO ; Untyped ;
; QUALIFY_CONF_DONE ; OFF ; Untyped ;
; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
; SCAN_CHAIN ; LONG ; Untyped ;
; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
; INCLK0_INPUT_FREQUENCY ; 20000 ; Signed Integer ;
; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
; GATE_LOCK_SIGNAL ; NO ; Untyped ;
; GATE_LOCK_COUNTER ; 0 ; Untyped ;
; LOCK_HIGH ; 1 ; Untyped ;
; LOCK_LOW ; 1 ; Untyped ;
; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
; SKIP_VCO ; OFF ; Untyped ;
; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
; BANDWIDTH ; 0 ; Untyped ;
; BANDWIDTH_TYPE ; AUTO ; Untyped ;
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